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cxp GW: add rtio chs

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morgan 2025-01-16 17:33:18 +08:00
parent a7345909c9
commit dbc00b1bcb
1 changed files with 15 additions and 13 deletions
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28
src/gateware/cxp.py
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@ -272,33 +272,35 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
# Trigger rtio
nbit_trigdelay = 8
nbit_linktrig = 1
self.rtlink = rtlink.Interface(
self.trigger = rtlink.Interface(
rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
rtlink.IInterface(word_width, timestamped=False)
)
self.sync.rio += [
If(self.rtlink.o.stb,
pipelines[master].tx.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
pipelines[master].tx.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
If(self.trigger.o.stb,
pipelines[master].tx.trig.delay.eq(self.trigger.o.data[nbit_linktrig:]),
pipelines[master].tx.trig.linktrig_mode.eq(self.trigger.o.data[:nbit_linktrig]),
),
pipelines[master].tx.trig.stb.eq(self.rtlink.o.stb),
pipelines[master].tx.trig.stb.eq(self.trigger.o.stb),
]
# ROI rtio
# # 4 cfg (x0, x1, y0, y1) per roi_engine
# self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
# 4 cfg (x0, y0, x1, y1) per roi_engine
self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
# # select which roi engine can output rtio_input signal
# self.gate_data = rtlink.Interface(
# rtlink.OInterface(roi_engine_count),
# # the 32th bits is for sentinel (gate detection)
# rtlink.IInterface(count_width+1, timestamped=False)
# )
# select which roi engine can output rtio_input signal
self.gate_data = rtlink.Interface(
rtlink.OInterface(roi_engine_count),
# the 32th bits is for sentinel (gate detection)
rtlink.IInterface(count_width+1, timestamped=False)
)
self.roi_counter = CSRStatus(count_width)
self.roi_update = CSR()
# # #
cdr = ClockDomainsRenamer("cxp_gtx_rx")