From dbc00b1bcbd1dbc8fcbb0aa508402dee5592fc43 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 16 Jan 2025 17:33:18 +0800
Subject: [PATCH] cxp GW: add rtio chs

---
 src/gateware/cxp.py | 28 +++++++++++++++-------------
 1 file changed, 15 insertions(+), 13 deletions(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index f18a863..ed26d9a 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -272,33 +272,35 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
         # Trigger rtio
         nbit_trigdelay = 8
         nbit_linktrig = 1
-        self.rtlink = rtlink.Interface(
+        self.trigger = rtlink.Interface(
             rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
             rtlink.IInterface(word_width, timestamped=False)
         )
 
         self.sync.rio += [
-            If(self.rtlink.o.stb,
-                pipelines[master].tx.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
-                pipelines[master].tx.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
+            If(self.trigger.o.stb,
+                pipelines[master].tx.trig.delay.eq(self.trigger.o.data[nbit_linktrig:]),
+                pipelines[master].tx.trig.linktrig_mode.eq(self.trigger.o.data[:nbit_linktrig]),
             ),
-            pipelines[master].tx.trig.stb.eq(self.rtlink.o.stb),
+            pipelines[master].tx.trig.stb.eq(self.trigger.o.stb),
         ]
 
 
         # ROI rtio
          
-        # # 4 cfg (x0, x1, y0, y1) per roi_engine
-        # self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
+        # 4 cfg (x0, y0, x1, y1) per roi_engine
+        self.config = rtlink.Interface(rtlink.OInterface(res_width, bits_for(4*roi_engine_count-1)))
 
-        # # select which roi engine can output rtio_input signal
-        # self.gate_data = rtlink.Interface(
-        #     rtlink.OInterface(roi_engine_count),
-        #     # the 32th bits is for sentinel (gate detection)
-        #     rtlink.IInterface(count_width+1, timestamped=False)
-        # )
+        # select which roi engine can output rtio_input signal
+        self.gate_data = rtlink.Interface(
+            rtlink.OInterface(roi_engine_count),
+            # the 32th bits is for sentinel (gate detection)
+            rtlink.IInterface(count_width+1, timestamped=False)
+        )
 
 
+        self.roi_counter = CSRStatus(count_width)
+        self.roi_update = CSR()
         # # #
         
         cdr = ClockDomainsRenamer("cxp_gtx_rx")