forked from M-Labs/artiq-zynq
cxp GW: use receiver path pipeline
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@ -23,21 +23,42 @@ class DownConn_Interface(Module, AutoCSR):
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self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.gtxs = phy.gtxs
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# TODO add mux here and fifos
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# decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
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# DEBUG: TX pipeline
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self.submodules.debug_src = debug_src = TX_Command_Packet()
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self.submodules.trig_ack = trig_ack = Trigger_ACK()
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self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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tx_pipeline = [debug_src, conv, phy.sinks[0]]
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self.ack = CSR()
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self.mux_sel = CSRStorage()
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self.sync += trig_ack.ack.eq(self.ack.re),
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self.comb += [
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debug_src.source.connect(mux.sink0),
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trig_ack.source.connect(mux.sink1),
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mux.sel.eq(self.mux_sel.storage)
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]
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tx_pipeline = [mux , conv, phy.sinks[0]]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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rx_pipeline = [phy.sources[0], debug_out]
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# NOTE: RX pipeline
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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self.submodules.recv_path = recv_path = Receiver_Path()
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rx_pipeline = [phy.sources[0], recv_path, debug_out]
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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# DEBUG: CSR
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self.trig_ack = CSRStatus()
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self.trig_clr = CSR()
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self.comb += [
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self.trig_ack.status.eq(recv_path.trig_ack),
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recv_path.trig_clr.eq(self.trig_clr.re),
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]
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class UpConn_Interface(Module, AutoCSR):
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def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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