From c74c1c2ac42d3dd8d512c80e1133d476849d011b Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 19 Sep 2024 14:39:28 +0800
Subject: [PATCH] cxp GW: use receiver path pipeline

---
 src/gateware/cxp.py | 33 +++++++++++++++++++++++++++------
 1 file changed, 27 insertions(+), 6 deletions(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 5adf5cd..177287b 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -23,21 +23,42 @@ class DownConn_Interface(Module, AutoCSR):
         self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
         self.gtxs = phy.gtxs
 
-        # TODO add mux here and fifos
-        # decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
-
+        # DEBUG: TX pipeline
         self.submodules.debug_src = debug_src = TX_Command_Packet()
+        self.submodules.trig_ack = trig_ack = Trigger_ACK()
+        self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
         self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
-        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
 
-        tx_pipeline = [debug_src, conv, phy.sinks[0]]
+        self.ack = CSR()
+        self.mux_sel = CSRStorage()
+        self.sync += trig_ack.ack.eq(self.ack.re),
+
+        self.comb += [
+            debug_src.source.connect(mux.sink0),
+            trig_ack.source.connect(mux.sink1),
+            mux.sel.eq(self.mux_sel.storage)
+        ]
+
+        tx_pipeline = [mux , conv, phy.sinks[0]]
         for s, d in zip(tx_pipeline, tx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
-        rx_pipeline = [phy.sources[0], debug_out]
+        # NOTE: RX pipeline
+        self.submodules.debug_out = debug_out = RX_Debug_Buffer()
+        self.submodules.recv_path = recv_path = Receiver_Path()
+
+        rx_pipeline = [phy.sources[0], recv_path, debug_out]
         for s, d in zip(rx_pipeline, rx_pipeline[1:]):
             self.comb += s.source.connect(d.sink)
 
+        # DEBUG: CSR
+        self.trig_ack = CSRStatus()
+        self.trig_clr = CSR()
+        self.comb += [
+            self.trig_ack.status.eq(recv_path.trig_ack),
+            recv_path.trig_clr.eq(self.trig_clr.re),
+        ]
+
         
 class UpConn_Interface(Module, AutoCSR):
     def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):