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cxp GW: use receiver path pipeline

This commit is contained in:
morgan 2024-09-19 14:39:28 +08:00
parent c83e31af7e
commit c74c1c2ac4
1 changed files with 27 additions and 6 deletions
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33
src/gateware/cxp.py
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@ -23,21 +23,42 @@ class DownConn_Interface(Module, AutoCSR):
self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.gtxs = phy.gtxs self.gtxs = phy.gtxs
# TODO add mux here and fifos # DEBUG: TX pipeline
# decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
self.submodules.debug_src = debug_src = TX_Command_Packet() self.submodules.debug_src = debug_src = TX_Command_Packet()
self.submodules.trig_ack = trig_ack = Trigger_ACK()
self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True) self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
self.submodules.debug_out = debug_out = RX_Debug_Buffer()
tx_pipeline = [debug_src, conv, phy.sinks[0]] self.ack = CSR()
self.mux_sel = CSRStorage()
self.sync += trig_ack.ack.eq(self.ack.re),
self.comb += [
debug_src.source.connect(mux.sink0),
trig_ack.source.connect(mux.sink1),
mux.sel.eq(self.mux_sel.storage)
]
tx_pipeline = [mux , conv, phy.sinks[0]]
for s, d in zip(tx_pipeline, tx_pipeline[1:]): for s, d in zip(tx_pipeline, tx_pipeline[1:]):
self.comb += s.source.connect(d.sink) self.comb += s.source.connect(d.sink)
rx_pipeline = [phy.sources[0], debug_out] # NOTE: RX pipeline
self.submodules.debug_out = debug_out = RX_Debug_Buffer()
self.submodules.recv_path = recv_path = Receiver_Path()
rx_pipeline = [phy.sources[0], recv_path, debug_out]
for s, d in zip(rx_pipeline, rx_pipeline[1:]): for s, d in zip(rx_pipeline, rx_pipeline[1:]):
self.comb += s.source.connect(d.sink) self.comb += s.source.connect(d.sink)
# DEBUG: CSR
self.trig_ack = CSRStatus()
self.trig_clr = CSR()
self.comb += [
self.trig_ack.status.eq(recv_path.trig_ack),
recv_path.trig_clr.eq(self.trig_clr.re),
]
class UpConn_Interface(Module, AutoCSR): class UpConn_Interface(Module, AutoCSR):
def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):