morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

upconn fw: refactor Control W/R packet

This commit is contained in:
morgan 2024-09-11 11:57:21 +08:00
parent 16ccd7eada
commit aeabca2182
1 changed files with 91 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

161
src/libboard_artiq/src/cxp_upconn.rs
View File

@ -6,6 +6,9 @@ use libboard_zynq::{println, timer::GlobalTimer};
use crate::pl::csr;
const MAX_PACKET: usize = 128;
const DATA_MAXSIZE: usize = /*max size*/MAX_PACKET - /*Tag*/4 - /*Op code & length*/4 - /*addr*/4 - /*CRC*/4 ;
#[derive(Debug)]
pub enum Error {
BufferError,
@ -19,7 +22,7 @@ impl From<IoError> for Error {
}
pub fn tx_test(timer: &mut GlobalTimer) {
const LEN: usize = 4 * 1000;
const LEN: usize = 4 * 50;
let mut pak_arr: [u8; LEN] = [0; LEN];
unsafe {
@ -27,12 +30,13 @@ pub fn tx_test(timer: &mut GlobalTimer) {
// csr::cxp::upconn_bitrate2x_enable_write(1);
csr::cxp::upconn_clk_reset_write(0);
// send(&Packet::ControlU32Reg(Command::Read { addr: 0x00 })).expect("Cannot send CoaXpress packet");
read_u32(0x00).expect("Cannot Write CoaXpress Register");
// csr::cxp::upconn_tx_testmode_en_write(1);
csr::cxp::upconn_tx_testmode_en_write(1);
csr::cxp::upconn_tx_enable_write(1);
timer.delay_us(2); // send one word
csr::cxp::upconn_testseq_stb_write(1);
// csr::cxp::upconn_testseq_stb_write(1);
// timer.delay_us(2);
// DEBUG: Trigger packet
@ -42,8 +46,8 @@ pub fn tx_test(timer: &mut GlobalTimer) {
// csr::cxp::upconn_trig_stb_write(1); // send trig
// DEBUG: Trigger ACK packet
// csr::cxp::upconn_ack_write(1);
timer.delay_us(2000);
csr::cxp::upconn_ack_write(1);
timer.delay_us(20);
csr::cxp::upconn_tx_enable_write(0);
// Collect data
@ -62,75 +66,63 @@ pub fn tx_test(timer: &mut GlobalTimer) {
}
}
pub enum Command<T> {
Read { addr: u32 },
Write { addr: u32, data: T },
ReadWithTag { addr: u32, tag: u8 },
WriteWithTag { addr: u32, data: T, tag: u8 },
}
pub enum Packet {
ControlU32Reg(Command<u32>),
ControlU64Reg(Command<u64>),
CtrlRead {
addr: u32,
length: u8,
},
CtrlWrite {
addr: u32,
length: u8,
data: [u8; DATA_MAXSIZE],
}, // max register size is 8 bytes
CtrlReadWithTag {
tag: u8,
addr: u32,
length: u8,
},
CtrlWriteWithTag {
tag: u8,
addr: u32,
length: u8,
data: [u8; DATA_MAXSIZE],
}, // max register size is 8 bytes
}
impl Packet {
pub fn write_to<W>(&self, writer: &mut W) -> Result<(), Error>
where W: Write {
// CoaXpress use big endian
match self {
Packet::ControlU32Reg(cmd) => match cmd {
Command::Read { addr } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x00, 0x00, 0x00, 0x04])?;
writer.write(&addr.to_be_bytes())?;
}
Command::Write { addr, data } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x01, 0x00, 0x00, 0x04])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data.to_be_bytes())?;
}
Command::ReadWithTag { addr, tag } => {
writer.write(&[0x05; 4])?;
writer.write(&[*tag; 4])?;
writer.write(&[0x00, 0x00, 0x00, 0x04])?;
writer.write(&addr.to_be_bytes())?;
}
Command::WriteWithTag { addr, data, tag } => {
writer.write(&[0x05; 4])?;
writer.write(&[*tag; 4])?;
writer.write(&[0x01, 0x00, 0x00, 0x04])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data.to_be_bytes())?;
}
},
Packet::ControlU64Reg(cmd) => match cmd {
Command::Read { addr } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x00, 0x00, 0x00, 0x08])?;
writer.write(&addr.to_be_bytes())?;
}
Command::Write { addr, data } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x01, 0x00, 0x00, 0x08])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data.to_be_bytes())?;
}
Command::ReadWithTag { addr, tag } => {
writer.write(&[0x05; 4])?;
writer.write(&[*tag; 4])?;
writer.write(&[0x00, 0x00, 0x00, 0x08])?;
writer.write(&addr.to_be_bytes())?;
}
Command::WriteWithTag { addr, data, tag } => {
writer.write(&[0x05; 4])?;
writer.write(&[*tag; 4])?;
writer.write(&[0x01, 0x00, 0x00, 0x08])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data.to_be_bytes())?;
}
},
match *self {
Packet::CtrlRead { addr, length } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x00, 0x00, 0x00, length])?;
writer.write(&addr.to_be_bytes())?;
}
Packet::CtrlWrite { addr, length, data } => {
writer.write(&[0x02; 4])?;
writer.write(&[0x01, 0x00, 0x00, length])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data[0..length as usize])?;
}
Packet::CtrlReadWithTag { tag, addr, length } => {
writer.write(&[0x05; 4])?;
writer.write(&[tag; 4])?;
writer.write(&[0x00, 0x00, 0x00, length])?;
writer.write(&addr.to_be_bytes())?;
}
Packet::CtrlWriteWithTag {
tag,
addr,
length,
data,
} => {
writer.write(&[0x05; 4])?;
writer.write(&[tag; 4])?;
writer.write(&[0x01, 0x00, 0x00, length])?;
writer.write(&addr.to_be_bytes())?;
writer.write(&data[0..length as usize])?;
}
}
Ok(())
}
@ -142,8 +134,7 @@ pub fn send(packet: &Packet) -> Result<(), Error> {
// Err(Error::LinkDown)?
// }
const LEN: usize = 4 * 20;
let mut buffer: [u8; LEN] = [0; LEN];
let mut buffer: [u8; MAX_PACKET] = [0; MAX_PACKET];
let mut writer = Cursor::new(&mut buffer[..]);
packet.write_to(&mut writer)?;
@ -166,6 +157,36 @@ pub fn send(packet: &Packet) -> Result<(), Error> {
Ok(())
}
pub fn write_u32(addr: u32, data: u32) -> Result<(), Error> {
let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
data_slice[..4].clone_from_slice(&data.to_be_bytes());
send(&Packet::CtrlWrite {
addr,
length: 4,
data: data_slice,
})?;
Ok(())
}
pub fn read_u32(addr: u32) -> Result<(), Error> {
send(&Packet::CtrlRead { addr, length: 4 })?;
Ok(())
}
pub fn write_u64(addr: u32, data: u64) -> Result<(), Error> {
let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
data_slice[..8].clone_from_slice(&data.to_be_bytes());
send(&Packet::CtrlWrite {
addr,
length: 8,
data: data_slice,
})?;
Ok(())
}
fn print_packet(pak: &[u8]) {
println!("pak = [");
for i in 0..(pak.len() / 4) {