morgan/artiq-zynq
1
0
Fork 0
forked from M-Labs/artiq-zynq
Code Pull Requests Activity

upconn GW: remove used debug port

Browse Source
This commit is contained in:
morgan 2025-01-16 11:14:08 +08:00
parent 8f75a820a7
commit a918fec3b0
1 changed files with 3 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gateware/cxp_upconn.py
View File

@ -62,10 +62,6 @@ class SERDES_10bits(Module):
tx_bitcount = Signal(max=10) tx_bitcount = Signal(max=10)
tx_reg = Signal(10) tx_reg = Signal(10)
# DEBUG:
self.o = Signal()
self.comb += self.o.eq(o)
self.specials += Instance("OBUF", i_I=o, o_O=pad), self.specials += Instance("OBUF", i_I=o, o_O=pad),
self.sync += [ self.sync += [
@ -86,7 +82,7 @@ class SERDES_10bits(Module):
] ]
class Transmitter(Module, AutoCSR): class Transmitter(Module, AutoCSR):
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, pad, sys_clk_freq):
self.bitrate2x_enable = Signal() self.bitrate2x_enable = Signal()
self.clk_reset = Signal() self.clk_reset = Signal()
self.enable = Signal() self.enable = Signal()
@ -129,7 +125,7 @@ class Transmitter(Module, AutoCSR):
] ]
class CXP_TXPHYs(Module, AutoCSR): class CXP_TXPHYs(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads): def __init__(self, pads, sys_clk_freq):
self.clk_reset = CSR() self.clk_reset = CSR()
self.bitrate2x_enable = CSRStorage() self.bitrate2x_enable = CSRStorage()
self.enable = CSRStorage() self.enable = CSRStorage()
@ -139,7 +135,7 @@ class CXP_TXPHYs(Module, AutoCSR):
self.phys = [] self.phys = []
for i, pad in enumerate(pads): for i, pad in enumerate(pads):
tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads) tx = Transmitter(pad, sys_clk_freq)
self.phys.append(tx) self.phys.append(tx)
setattr(self.submodules, "tx"+str(i), tx) setattr(self.submodules, "tx"+str(i), tx)
self.sync += [ self.sync += [