diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py
index 81d39bb..c34a32d 100644
--- a/src/gateware/cxp_upconn.py
+++ b/src/gateware/cxp_upconn.py
@@ -62,10 +62,6 @@ class SERDES_10bits(Module):
         tx_bitcount = Signal(max=10)
         tx_reg = Signal(10)
 
-        # DEBUG:
-        self.o = Signal()
-        self.comb += self.o.eq(o)
-
         self.specials += Instance("OBUF", i_I=o, o_O=pad),
         
         self.sync += [
@@ -86,7 +82,7 @@ class SERDES_10bits(Module):
         ]
 
 class Transmitter(Module, AutoCSR):
-    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
+    def __init__(self, pad, sys_clk_freq):
         self.bitrate2x_enable = Signal()
         self.clk_reset = Signal()
         self.enable = Signal()
@@ -129,7 +125,7 @@ class Transmitter(Module, AutoCSR):
         ]
 
 class CXP_TXPHYs(Module, AutoCSR):
-    def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
+    def __init__(self, pads, sys_clk_freq):
         self.clk_reset = CSR()
         self.bitrate2x_enable = CSRStorage()
         self.enable = CSRStorage()
@@ -139,7 +135,7 @@ class CXP_TXPHYs(Module, AutoCSR):
 
         self.phys = []
         for i, pad in enumerate(pads):
-            tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
+            tx = Transmitter(pad, sys_clk_freq)
             self.phys.append(tx)
             setattr(self.submodules, "tx"+str(i), tx)
             self.sync += [