forked from M-Labs/artiq-zynq
zc706: use single lane cxp grabber
This commit is contained in:
parent
1fc3181fca
commit
a7be568b38
@ -688,7 +688,7 @@ class CXP_FMC():
|
|||||||
|
|
||||||
clk_freq = 125e6
|
clk_freq = 125e6
|
||||||
|
|
||||||
links = 4
|
links = 1
|
||||||
master_ch = 0
|
master_ch = 0
|
||||||
cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
|
cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
|
||||||
cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
|
cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
|
||||||
@ -732,7 +732,7 @@ class CXP_FMC():
|
|||||||
self.add_memory_group("cxp_mem", cxp_mem_group)
|
self.add_memory_group("cxp_mem", cxp_mem_group)
|
||||||
self.add_csr_group("cxp", cxp_csr_group)
|
self.add_csr_group("cxp", cxp_csr_group)
|
||||||
|
|
||||||
self.submodules.cxp_frame_pipeline = cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_core_pipelines, pmod_pads, master=master_ch)
|
self.submodules.cxp_frame_pipeline = cxp_frame_pipeline = cxp.CXP_Grabber(cxp_core_pipelines[0])
|
||||||
self.csr_devices.append("cxp_frame_pipeline")
|
self.csr_devices.append("cxp_frame_pipeline")
|
||||||
|
|
||||||
print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
|
print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
|
||||||
|
Loading…
Reference in New Issue
Block a user