forked from M-Labs/artiq-zynq
cxp GW: add cxp grabber properly
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@ -1,6 +1,7 @@
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from migen import *
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from migen.genlib.cdc import MultiReg, PulseSynchronizer
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from misoc.interconnect.csr import *
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from misoc.interconnect.stream import Buffer
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from misoc.cores.coaxpress.core import HostTXCore, HostRXCore
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from misoc.cores.coaxpress.phy.high_speed_gtx import HostRXPHYs
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from misoc.cores.coaxpress.phy.low_speed_serdes import HostTXPHYs
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@ -9,8 +10,6 @@ from artiq.gateware.rtio import rtlink
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from cxp_frame_pipeline import *
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import cxp_router
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from types import SimpleNamespace
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class CXP_Host_PHYS(Module, AutoCSR):
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@ -285,29 +284,37 @@ class CXP_Frame_Pipeline(Module, AutoCSR):
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# Instance("OBUF", i_I=arbiter.sinks[i].stb, o_O=pmod_pads[i]),
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]
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class NEO_CXP_Frame_pipeline(Module):
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class CXP_Grabber(Module, AutoCSR):
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# optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
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def __init__(self, pipelines, pmod_pads, roi_engine_count=1, res_width=16, count_width=31, master=0, packet_size=16384):
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n_channels = len(pipelines)
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assert n_channels > 0
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def __init__(self, host, roi_engine_count=1, res_width=16, count_width=31):
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assert count_width <= 31
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self.crc_error_cnt = CSRStatus(16)
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self.crc_error_reset = CSR()
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self.roi_counter = CSRStatus(count_width)
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self.roi_update = CSR()
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self.pix_y = CSRStatus(res_width)
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self.header_l_size = CSRStatus(3*char_width)
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self.header_x_size = CSRStatus(3*char_width)
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self.header_y_size = CSRStatus(3*char_width)
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self.header_new_line = CSRStatus(3*char_width)
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# # #
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# Trigger rtio
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nbit_trigdelay = 8
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nbit_linktrig = 1
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self.trigger = rtlink.Interface(
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rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
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rtlink.IInterface(word_width, timestamped=False)
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)
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self.trigger = rtlink.Interface(rtlink.OInterface(nbit_trigdelay + nbit_linktrig))
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self.sync.rio += [
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If(self.trigger.o.stb,
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pipelines[master].tx.trig.delay.eq(self.trigger.o.data[nbit_linktrig:]),
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pipelines[master].tx.trig.linktrig_mode.eq(self.trigger.o.data[:nbit_linktrig]),
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host.tx.trig_delay.eq(self.trigger.o.data[nbit_linktrig:]),
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host.tx.trig_linktrigger_mode.eq(self.trigger.o.data[:nbit_linktrig]),
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),
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pipelines[master].tx.trig.stb.eq(self.trigger.o.stb),
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host.tx.trig_stb.eq(self.trigger.o.stb),
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]
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# ROI rtio
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@ -325,24 +332,103 @@ class NEO_CXP_Frame_pipeline(Module):
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# # #
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cdr = ClockDomainsRenamer("cxp_gt_rx")
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debug_out = False
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if debug_out:
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pass
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#
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# downconn pipline -----> router -----> arbiter ------> crc checker ------> 4x converters
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# 32+8(dchar) 4 pixel
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# HostRXCore ─────/─────> Stream broadcaster ────> buffer ────> Pixel Core ───/───> Roi engines
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#
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# that drops the K29.7 and mark eop on the crc word
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self.submodules.broadcaster = broadcaster = cdr(Stream_Broadcaster())
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self.submodules.buffer = buffer = cdr(Buffer(word_layout_dchar)) # to improve timinig
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self.submodules.conv = conv = cdr(Stream2Pixel4x_Converter(res_width, count_width))
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# CRC error counter
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self.submodules.crc_reset_ps = crc_reset_ps = PulseSynchronizer("sys", "cxp_gt_rx")
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self.comb += crc_reset_ps.i.eq(self.crc_error_reset.re)
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# Connect pipeline
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for i, p in enumerate(pipelines):
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broadcaster = cdr(cxp_router.Stream_Router()) # strip the packet id, tag & packet size
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crc_checker = cdr(CXPCRC32_Checker())
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self.submodules += broadcaster, crc_checker
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crc_error_cnt_rx = Signal.like(self.crc_error_cnt.status)
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crc_error_r = Signal()
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self.sync.cxp_gt_rx += [
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# to improve timinig
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crc_error_r.eq(conv.crc_checker.error),
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self.comb += [
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p.rx.source.connect(broadcaster.sink),
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broadcaster.sources[0].connect(crc_checker),
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If(crc_reset_ps.o,
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crc_error_cnt_rx.eq(crc_error_cnt_rx.reset),
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).Elif(crc_error_r,
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crc_error_cnt_rx.eq(crc_error_cnt_rx + 1),
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),
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]
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self.specials += MultiReg(crc_error_cnt_rx, self.crc_error_cnt.status)
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# Connecting the pipeline
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self.comb += [
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host.rx.source.connect(broadcaster.sink),
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broadcaster.sources[0].connect(buffer.sink),
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buffer.source.connect(conv.sink),
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]
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roi_engines = [cdr(ROI(conv.pixel4x, count_width)) for _ in range(roi_engine_count)]
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self.submodules += roi_engines
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for n, roi in enumerate(roi_engines):
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cfg = roi.cfg
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for offset, target in enumerate([cfg.x0, cfg.y0, cfg.x1, cfg.y1]):
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roi_boundary = Signal.like(target)
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self.sync.rio += If(self.config.o.stb & (self.config.o.address == 4*n+offset),
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roi_boundary.eq(self.config.o.data))
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self.specials += MultiReg(roi_boundary, target, "cxp_gt_rx")
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roi_out = roi.out
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update = Signal()
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self.submodules.ps = ps = PulseSynchronizer("cxp_gt_rx", "sys")
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self.sync.cxp_gt_rx += ps.i.eq(roi_out.update)
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self.sync += update.eq(ps.o)
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sentinel = 2**count_width
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count_sys = Signal.like(roi_out.count)
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self.specials += MultiReg(roi_out.count, count_sys),
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self.sync.rio += [
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# TODO: add gating
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self.gate_data.i.stb.eq(update),
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# without the slice, unspecified bits will be 1 for some reason
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# i.e. data[count_wdith:] = 0b111111... when using data.eq(count_sys)
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self.gate_data.i.data[:count_width].eq(count_sys),
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]
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# DEBUG:
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new_line_cnt_rx, new_line_cnt_sys = Signal(3*char_width), Signal(3*char_width)
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l_size_rx, l_size_sys = Signal(3*char_width), Signal(3*char_width)
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x_size_rx, x_size_sys = Signal(3*char_width), Signal(3*char_width)
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y_size_rx, y_size_sys = Signal(3*char_width), Signal(3*char_width)
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y_pix_rx, y_pix_sys = Signal(res_width), Signal(res_width)
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self.sync.cxp_gt_rx += [
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If(conv.header_reader.new_line,
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new_line_cnt_rx.eq(new_line_cnt_rx + 1),
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),
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l_size_rx.eq(conv.header_reader.metadata.l_size),
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x_size_rx.eq(conv.header_reader.metadata.x_size),
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y_size_rx.eq(conv.header_reader.metadata.y_size),
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y_pix_rx.eq(conv.pixel4x[0].y),
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]
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self.specials += [
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MultiReg(new_line_cnt_rx, new_line_cnt_sys),
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MultiReg(l_size_rx, l_size_sys),
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MultiReg(x_size_rx, x_size_sys),
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MultiReg(y_size_rx, y_size_sys),
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MultiReg(y_pix_rx, y_pix_sys),
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]
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self.sync += [
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self.header_new_line.status.eq(new_line_cnt_sys),
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self.pix_y.status.eq(y_pix_sys),
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self.header_l_size.status.eq(l_size_sys),
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self.header_x_size.status.eq(x_size_sys),
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self.header_y_size.status.eq(y_size_sys),
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self.roi_counter.status.eq(count_sys),
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If(update,
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self.roi_update.w.eq(1),
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).Elif(self.roi_update.re,
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self.roi_update.w.eq(0),
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),
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]
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