forked from M-Labs/artiq-zynq
zc706: use single lane cxp grabber
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@ -688,7 +688,7 @@ class CXP_FMC():
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clk_freq = 125e6
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links = 4
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links = 1
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master_ch = 0
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cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
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cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
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@ -732,7 +732,7 @@ class CXP_FMC():
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self.add_memory_group("cxp_mem", cxp_mem_group)
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self.add_csr_group("cxp", cxp_csr_group)
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self.submodules.cxp_frame_pipeline = cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_core_pipelines, pmod_pads, master=master_ch)
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self.submodules.cxp_frame_pipeline = cxp_frame_pipeline = cxp.CXP_Grabber(cxp_core_pipelines[0])
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self.csr_devices.append("cxp_frame_pipeline")
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print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
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