forked from M-Labs/artiq-zynq
cxp: use designated Packet start inserter
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@ -4,7 +4,7 @@ from misoc.interconnect import stream
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from cxp_downconn import CXP_DownConn
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from cxp_upconn import CXP_UpConn
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from cxp_pipeline import Code_Inserter, CXPCRC32Inserter
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from cxp_pipeline import *
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class CXP(Module, AutoCSR):
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def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
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@ -76,11 +76,6 @@ class UpConn_Packets(Module, AutoCSR):
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]
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# TODO: put these stuff properly instead of declaring everytime
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def K(x, y):
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return [((y << 5) | x), 1]
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def D(x, y):
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return [((y << 5) | x), 0]
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def cxp_phy_layout():
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return [("data", 8), ("k", 1)]
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@ -107,7 +102,7 @@ class CXP_TX_Core(Module, AutoCSR):
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self.submodules.buf_in = buf_in = stream.SyncFIFO(cxp_phy_layout(), 2)
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self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64)
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self.submodules.pak_start = pak_start = Code_Inserter(*K(27, 7), cxp_phy_layout())
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self.submodules.pak_start = pak_start = Packet_Start_Inserter(cxp_phy_layout())
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self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout())
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self.sync += [
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@ -135,7 +130,7 @@ class CXP_TX_Core(Module, AutoCSR):
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]
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tx_pipeline = [ buf_in, crc_inserters, buf_out]
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tx_pipeline = [ buf_in, crc_inserters, pak_start, buf_out]
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for s, d in zip(tx_pipeline, tx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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