From a1d644279ee05b4cb67568753e317d7a047c2c0f Mon Sep 17 00:00:00 2001 From: morgan Date: Fri, 30 Aug 2024 13:17:13 +0800 Subject: [PATCH] cxp: use designated Packet start inserter --- src/gateware/cxp.py | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index 1891ea6..b8ded6f 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -4,7 +4,7 @@ from misoc.interconnect import stream from cxp_downconn import CXP_DownConn from cxp_upconn import CXP_UpConn -from cxp_pipeline import Code_Inserter, CXPCRC32Inserter +from cxp_pipeline import * class CXP(Module, AutoCSR): def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads): @@ -76,11 +76,6 @@ class UpConn_Packets(Module, AutoCSR): ] # TODO: put these stuff properly instead of declaring everytime -def K(x, y): - return [((y << 5) | x), 1] - -def D(x, y): - return [((y << 5) | x), 0] def cxp_phy_layout(): return [("data", 8), ("k", 1)] @@ -107,7 +102,7 @@ class CXP_TX_Core(Module, AutoCSR): self.submodules.buf_in = buf_in = stream.SyncFIFO(cxp_phy_layout(), 2) self.submodules.buf_out = buf_out = stream.SyncFIFO(cxp_phy_layout(), 64) - self.submodules.pak_start = pak_start = Code_Inserter(*K(27, 7), cxp_phy_layout()) + self.submodules.pak_start = pak_start = Packet_Start_Inserter(cxp_phy_layout()) self.submodules.crc_inserter = crc_inserters = CXPCRC32Inserter(cxp_phy_layout()) self.sync += [ @@ -135,7 +130,7 @@ class CXP_TX_Core(Module, AutoCSR): ] - tx_pipeline = [ buf_in, crc_inserters, buf_out] + tx_pipeline = [ buf_in, crc_inserters, pak_start, buf_out] for s, d in zip(tx_pipeline, tx_pipeline[1:]): self.comb += s.source.connect(d.sink)