zc706 GW: add CXP to rtio_channels

zc706: update fn names

zc706: use cxp_gtx_rxi clk

src/gateware/zc706.py

@@ -704,6 +704,7 @@ class CXP_FMC():
         self.csr_devices.append("cxp_phys")
 
 
+        rtio_channels = []
         cxp_csr_group = []
         cxp_tx_mem_group = []
         cxp_rx_mem_group = []
@@ -711,13 +712,25 @@ class CXP_FMC():
         for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
             cxp_name = "cxp" + str(i)
 
-            # TODO: cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
+            cdr = ClockDomainsRenamer({"cxp_gtx_rx": "cxp_gtx_rx" + str(i)})
+            
+            if i == 0:
+                cxp_interface = cdr(cxp.CXP_Master(tx, rx, debug_sma_pad, pmod_pads))
+
+                # Add rtlink for Master Connection only
+                print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+                rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
+
+            else:
+                cxp_interface = cdr(cxp.CXP_Extension(tx, rx, debug_sma_pad, pmod_pads))
 
-            cxp_interface = cxp.CXP_Interface(tx, rx, debug_sma_pad, pmod_pads)
             setattr(self.submodules, cxp_name, cxp_interface)
             self.csr_devices.append(cxp_name)
             cxp_csr_group.append(cxp_name)
 
+
+
+            # Add memory group
             rx_mem_name = "cxp_rx" + str(i) + "_mem"
             rx_mem_size = cxp_interface.get_rx_mem_size()
             cxp_rx_mem_group.append(rx_mem_name)
@@ -751,7 +764,6 @@ class CXP_FMC():
             # constraint the CLK path 
             platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
 
-        rtio_channels = []
         # FIXME remove this placeholder RTIO channel
         # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
         # see https://github.com/m-labs/artiq/pull/2158 for similar issue