morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

cxp: add linklayer upconn proto

This commit is contained in:
morgan 2024-08-27 11:15:09 +08:00
parent e78d0f4083
commit 868ac41060
1 changed files with 42 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

44
src/gateware/cxp.py
View File

@ -8,14 +8,54 @@ from cxp_upconn import CXP_UpConn
class CXP(Module, AutoCSR):
def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
self.submodules.crc = CXP_CRC(8)
# self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.submodules.upconn = LinkLayer_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
# TODO: support the option high speed upconn
# TODO: add link layer
class LinkLayer_UpConn(Module, AutoCSR):
def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
self.clk_reset = CSRStorage(reset=1)
self.bitrate2x_enable = CSRStorage()
self.tx_enable = CSRStorage()
# # #
self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, 32)
self.comb += [
upconn.clk_reset.eq(self.clk_reset.storage),
upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
upconn.tx_enable.eq(self.tx_enable.storage),
]
# Packets
# FIFOs with transmission priority
# 0: Trigger packet
# 1: IO acknowledgment for trigger packet
# 2: All other packets
self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.symbol0 = CSR(9)
self.symbol1 = CSR(9)
self.symbol2 = CSR(9)
self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
self.sync += [
upconn.tx_fifos.sink_stb[0].eq(self.symbol0.re),
upconn.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
upconn.tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
upconn.tx_fifos.sink_stb[1].eq(self.symbol1.re),
upconn.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
upconn.tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
upconn.tx_fifos.sink_stb[2].eq(self.symbol2.re),
upconn.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
]
class CXP_CRC(Module, AutoCSR):
width = 32