From 868ac4106080cdda86450e15bf8def7728842630 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Tue, 27 Aug 2024 11:15:09 +0800
Subject: [PATCH] cxp: add linklayer upconn proto

---
 src/gateware/cxp.py | 44 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 42 insertions(+), 2 deletions(-)

diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py
index 56837ad..4313201 100644
--- a/src/gateware/cxp.py
+++ b/src/gateware/cxp.py
@@ -8,14 +8,54 @@ from cxp_upconn import CXP_UpConn
 class CXP(Module, AutoCSR):
     def __init__(self, refclk, downconn_pads, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
         self.submodules.crc = CXP_CRC(8)
+        # self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.submodules.upconn = LinkLayer_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
+        self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        # TODO: support the option high speed upconn
+
+        # TODO: add link layer
+
+        
+class LinkLayer_UpConn(Module, AutoCSR):
+    def __init__(self, upconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.clk_reset = CSRStorage(reset=1)
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+
+        # # #
+
+        self.submodules.upconn = upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, 32)
+
+        self.comb += [
+            upconn.clk_reset.eq(self.clk_reset.storage),
+            upconn.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
+            upconn.tx_enable.eq(self.tx_enable.storage),
+        ]
+
+
+        # Packets
         # FIFOs with transmission priority
         # 0: Trigger packet
         # 1: IO acknowledgment for trigger packet
         # 2: All other packets
-        self.submodules.upconn = CXP_UpConn(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.symbol0 = CSR(9)
+        self.symbol1 = CSR(9)
+        self.symbol2 = CSR(9)
 
-        self.submodules.downconn = CXP_DownConn(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.sync += [
+            upconn.tx_fifos.sink_stb[0].eq(self.symbol0.re),
+            upconn.tx_fifos.sink_data[0].eq(self.symbol0.r[:8]),
+            upconn.tx_fifos.sink_k[0].eq(self.symbol0.r[8]),
 
+            upconn.tx_fifos.sink_stb[1].eq(self.symbol1.re),
+            upconn.tx_fifos.sink_data[1].eq(self.symbol1.r[:8]),
+            upconn.tx_fifos.sink_k[1].eq(self.symbol1.r[8]),
+
+            upconn.tx_fifos.sink_stb[2].eq(self.symbol2.re),
+            upconn.tx_fifos.sink_data[2].eq(self.symbol2.r[:8]),
+            upconn.tx_fifos.sink_k[2].eq(self.symbol2.r[8]),
+        ]
 
 class CXP_CRC(Module, AutoCSR):
     width = 32