morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

downconn GW: move cdc fifo out of phy

This commit is contained in:
morgan 2024-10-02 17:42:06 +08:00
parent ad8260d93a
commit 7b0f94674e
1 changed files with 9 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/gateware/cxp_downconn.py
View File

@ -45,22 +45,15 @@ class Receiver(Module):
def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads): def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single") self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single")
# DEBUG: remove cdc rx fifo self.source = stream.Endpoint(word_layout)
# gtx rx -> fifo out -> cdc out
rx_fifo = stream.AsyncFIFO(word_layout, 512)
self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(rx_fifo)
self.source = rx_fifo.source
for i in range(4):
self.sync.cxp_gtx_rx += [ self.sync.cxp_gtx_rx += [
rx_fifo.sink.stb.eq(0), self.source.stb.eq(0),
# don't store idle word in fifo If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
If((gtx.rx_ready & rx_fifo.sink.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))), self.source.stb.eq(1),
rx_fifo.sink.stb.eq(1), self.source.data.eq(Cat(gtx.decoders[0].d, gtx.decoders[1].d, gtx.decoders[2].d, gtx.decoders[3].d)),
rx_fifo.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d), self.source.k.eq(Cat(gtx.decoders[0].k, gtx.decoders[1].k, gtx.decoders[2].k, gtx.decoders[3].k)),
rx_fifo.sink.k[i].eq(gtx.decoders[i].k), )
),
] ]
# DEBUG: tx fifos for loopback # DEBUG: tx fifos for loopback