From 7b0f94674eb53ec6d0388990ab8950ca4f82e698 Mon Sep 17 00:00:00 2001 From: morgan Date: Wed, 2 Oct 2024 17:42:06 +0800 Subject: [PATCH] downconn GW: move cdc fifo out of phy --- src/gateware/cxp_downconn.py | 25 +++++++++---------------- 1 file changed, 9 insertions(+), 16 deletions(-) diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py index 9288bbe..56ad75a 100644 --- a/src/gateware/cxp_downconn.py +++ b/src/gateware/cxp_downconn.py @@ -45,23 +45,16 @@ class Receiver(Module): def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads): self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode="single", rx_mode="single") - # DEBUG: remove cdc rx fifo - # gtx rx -> fifo out -> cdc out - - rx_fifo = stream.AsyncFIFO(word_layout, 512) - self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(rx_fifo) - self.source = rx_fifo.source + self.source = stream.Endpoint(word_layout) - for i in range(4): - self.sync.cxp_gtx_rx += [ - rx_fifo.sink.stb.eq(0), - # don't store idle word in fifo - If((gtx.rx_ready & rx_fifo.sink.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1))), - rx_fifo.sink.stb.eq(1), - rx_fifo.sink.data[i*8:(i*8)+8].eq(gtx.decoders[i].d), - rx_fifo.sink.k[i].eq(gtx.decoders[i].k), - ), - ] + self.sync.cxp_gtx_rx += [ + self.source.stb.eq(0), + If(gtx.rx_ready & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)), + self.source.stb.eq(1), + self.source.data.eq(Cat(gtx.decoders[0].d, gtx.decoders[1].d, gtx.decoders[2].d, gtx.decoders[3].d)), + self.source.k.eq(Cat(gtx.decoders[0].k, gtx.decoders[1].k, gtx.decoders[2].k, gtx.decoders[3].k)), + ) + ] # DEBUG: tx fifos for loopback # fw -> fifo (sys) -> cdc fifo -> gtx tx