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downconn GW: update docs

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morgan 2025-01-17 13:36:48 +08:00
parent ee3cac1efb
commit 7a8e967e77
1 changed files with 10 additions and 6 deletions
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16
src/gateware/cxp_downconn.py
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@ -581,10 +581,12 @@ class GTX(Module):
# TX clocking # TX clocking
# As TX buffer is bypass, freq txoutclk_buf == refclk # When bypassing the TX buffer and changing frequency of VCO of QPLL/CPLL,
# To match the require frequency TXUSRCLK = linerate/datewidth (UG476 Equation 3-1) # TXUSRCLK rate will always be the refclk rate.
# A PLL need to be used to generate the correct frequency for TXUSRCLK # To match the required TXUSRCLK rate = linerate/datewidth (UG476 (v1.12.1) Equation 3-1), a DRP PLL is used.
if tx_mode:
# Slave TX will use cxp_gtx_tx from master
if tx_mode == "single" or tx_mode == "master":
self.clock_domains.cd_cxp_gtx_tx = ClockDomain() self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
txpll_fb_clk = Signal() txpll_fb_clk = Signal()
txoutclk_buf = Signal() txoutclk_buf = Signal()
@ -635,8 +637,10 @@ class GTX(Module):
self.comb += tx_init.restart.eq(self.tx_restart) self.comb += tx_init.restart.eq(self.tx_restart)
# RX clocking # RX clocking
# the CDR matches the required frequency for RXUSRCLK, no need for PLL # When frequency of VCO of QPLL/CPLL is changed, RXUSRCLK will match the required frequency
# Slave Rx will use cxp_gtx_rx from master # RXUSRCLK rate = linerate/datewidth (UG476 (v1.12.1) Equation 4-2). And PLL is not needed.
# Slave RX will use cxp_gtx_rx from master
if rx_mode == "single" or rx_mode == "master": if rx_mode == "single" or rx_mode == "master":
self.clock_domains.cd_cxp_gtx_rx = ClockDomain() self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
self.specials += [ self.specials += [