From 7a8e967e77a9034fdad279529ca5abe75785ab85 Mon Sep 17 00:00:00 2001 From: morgan Date: Fri, 17 Jan 2025 13:36:48 +0800 Subject: [PATCH] downconn GW: update docs --- src/gateware/cxp_downconn.py | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/src/gateware/cxp_downconn.py b/src/gateware/cxp_downconn.py index 45a1e5b..f5b9c66 100644 --- a/src/gateware/cxp_downconn.py +++ b/src/gateware/cxp_downconn.py @@ -581,10 +581,12 @@ class GTX(Module): # TX clocking - # As TX buffer is bypass, freq txoutclk_buf == refclk - # To match the require frequency TXUSRCLK = linerate/datewidth (UG476 Equation 3-1) - # A PLL need to be used to generate the correct frequency for TXUSRCLK - if tx_mode: + # When bypassing the TX buffer and changing frequency of VCO of QPLL/CPLL, + # TXUSRCLK rate will always be the refclk rate. + # To match the required TXUSRCLK rate = linerate/datewidth (UG476 (v1.12.1) Equation 3-1), a DRP PLL is used. + + # Slave TX will use cxp_gtx_tx from master + if tx_mode == "single" or tx_mode == "master": self.clock_domains.cd_cxp_gtx_tx = ClockDomain() txpll_fb_clk = Signal() txoutclk_buf = Signal() @@ -635,8 +637,10 @@ class GTX(Module): self.comb += tx_init.restart.eq(self.tx_restart) # RX clocking - # the CDR matches the required frequency for RXUSRCLK, no need for PLL - # Slave Rx will use cxp_gtx_rx from master + # When frequency of VCO of QPLL/CPLL is changed, RXUSRCLK will match the required frequency + # RXUSRCLK rate = linerate/datewidth (UG476 (v1.12.1) Equation 4-2). And PLL is not needed. + + # Slave RX will use cxp_gtx_rx from master if rx_mode == "single" or rx_mode == "master": self.clock_domains.cd_cxp_gtx_rx = ClockDomain() self.specials += [