cxp upconn: setup fifo

src/gateware/cxp_upconn.py

@@ -7,7 +7,7 @@ from misoc.interconnect.csr import *
 from misoc.interconnect import stream
 
 class CXP_UpConn(Module, AutoCSR):
-    def __init__(self, pads, tx_width=10):
+    def __init__(self, pads, tx_width=10, tx_fifo_depth=16):
         self.clock_domains.cd_cxp_upconn = ClockDomain()
         self.clk_reset = CSRStorage(reset=1)
 
@@ -48,37 +48,80 @@ class CXP_UpConn(Module, AutoCSR):
             AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
         ]
 
-        self.stb = CSRStorage()
-        self.data = CSRStorage(8)
-        self.k_symbol = CSRStorage()
+        self.symbol = CSR(9)
         self.encoded = CSRStatus(tx_width)
         self.tx_reg = CSRStatus(tx_width)
 
+        self.data = Signal(8)
+        self.k_symbol = Signal()
+        self.stb = Signal()
+        
+        nfifos = 1
+       
+        self.fifo_full = CSRStatus(nfifos)
+
+
+        self.tx_fifos = []
+        self.tx_encoders = []
+
+        cdr = ClockDomainsRenamer({"write": "sys", "read": "cxp_upconn"})
+
+        # Priority Queue
+        for i in range(nfifos):
+            fifo = cdr(stream.AsyncFIFO([("data", 9)], tx_fifo_depth))
+            self.tx_fifos.append(fifo)
+            setattr(self.submodules, "tx_fifo" + str(i), fifo)
+            self.sync += [
+                fifo.sink.stb.eq(self.stb),
+                fifo.sink.data.eq(Cat(self.data, self.k_symbol)),
+                self.fifo_full.status[i].eq(~fifo.sink.ack),
+                self.stb.eq(self.symbol.re),
+                self.data.eq(self.symbol.r[:8]),
+                self.k_symbol.eq(self.symbol.r[8])
+            ]
+
+        self.tx_fifo0_source_data = CSRStatus(9)        
+
+        self.submodules.encoder = SingleEncoder(True)
+
+        tx_busy = Signal()
+        data_ack = Signal()
+        data_stb = Signal()
+
+        self.comb += [
+            data_stb.eq(self.tx_fifos[0].source.stb),
+            If(self.tx_fifos[0].source.stb,
+                self.encoder.d.eq(self.tx_fifos[0].source.data[:8]),
+                self.encoder.k.eq(self.tx_fifos[0].source.data[8]),
+                self.tx_fifos[0].source.ack.eq(data_ack),
+            ),
+            # TODO: add idle & other fifo here
+            self.tx_fifo0_source_data.status.eq(self.tx_fifos[0].source.data)
+        ]
 
         o = Signal()
         tx_bitcount = Signal(max=tx_width)
         tx_reg = Signal(tx_width)
 
-        self.submodules.encoder = SingleEncoder(True)
-
-        self.comb += [
-            self.encoder.d.eq(self.data.storage),
-            self.encoder.k.eq(self.k_symbol.storage),
-        ]
-
         self.sync.cxp_upconn +=[
             self.encoded.status.eq(self.encoder.output),
-            If(self.stb.storage,
+            data_ack.eq(0),
+            If(tx_busy,
                 o.eq(tx_reg[0]),
                 tx_reg.eq(Cat(tx_reg[1:], 0))
             ),
             If(tx_bitcount != tx_width - 1,
                 tx_bitcount.eq(tx_bitcount + 1),   
-            ).Elif(self.stb.storage,
+            ).Elif(data_stb,
+                tx_busy.eq(1),
                 tx_bitcount.eq(0),
                 tx_reg.eq(self.encoder.output),
                 self.tx_reg.status.eq(self.encoder.output),
                 self.encoder.disp_in.eq(self.encoder.disp_out),
+                data_ack.eq(1),
+            ).Else(
+                tx_busy.eq(0),
+                o.eq(0)
             )
         ]