forked from M-Labs/artiq-zynq
cxp upconn: add upconn pads & cleanup
cxp upconn: cleanup
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0cf8cd42d5
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@ -8,8 +8,7 @@ from misoc.interconnect.csr import *
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class CXP_UpConn(Module, AutoCSR):
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nfifos = 3
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def __init__(self, pads, sys_clk_freq, pmod, fifo_depth=32):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3):
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self.clock_domains.cd_cxp_upconn = ClockDomain()
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self.clk_reset = CSRStorage(reset=1)
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self.bitrate2x_enable = CSRStorage()
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@ -50,11 +49,14 @@ class CXP_UpConn(Module, AutoCSR):
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AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage)
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]
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self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.startup_fsm = startup_fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE"))
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self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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self.submodules.tx_fifos = tx_fifos = TxFIFOs(self.nfifos, fifo_depth)
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self.submodules.tx_idle = tx_idle = TxIdle()
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o = Signal()
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self.specials += Instance("OBUF", i_I=o, o_O=pad),
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tx_en = Signal()
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tx_bitcount = Signal(max=10)
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tx_charcount = Signal(max=4)
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@ -64,24 +66,22 @@ class CXP_UpConn(Module, AutoCSR):
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priorities = Signal(max=self.nfifos)
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idling = Signal()
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self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True))
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# startup sequence
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self.fsm.act("WAIT_TX_ENABLE",
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startup_fsm.act("WAIT_TX_ENABLE",
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If(self.tx_enable.storage,
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NextValue(tx_idle.word_idx, 0),
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NextState("ENCODE_CHAR")
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)
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)
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self.fsm.act("ENCODE_CHAR",
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startup_fsm.act("ENCODE_CHAR",
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NextValue(tx_idle.source_ack, 1),
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NextValue(encoder.d, tx_idle.source_data),
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NextValue(encoder.k, tx_idle.source_k),
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NextState("LOAD_CHAR"),
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)
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self.fsm.act("LOAD_CHAR",
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startup_fsm.act("LOAD_CHAR",
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NextValue(idling, 1),
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NextValue(tx_charcount, 0),
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NextValue(tx_bitcount, 0),
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@ -91,7 +91,7 @@ class CXP_UpConn(Module, AutoCSR):
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NextState("START_TX")
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)
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self.fsm.act("START_TX",
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startup_fsm.act("START_TX",
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tx_en.eq(1),
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If((~self.tx_enable.storage) & (tx_charcount == 3),
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NextState("WAIT_TX_ENABLE")
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@ -183,21 +183,21 @@ class CXP_UpConn(Module, AutoCSR):
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]
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self.specials += [
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# # debug sma
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# Instance("OBUF", i_I=o, o_O=pads.p_tx),
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# Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx),
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Instance("OBUF", i_I=o, o_O=debug_sma.p_tx),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=debug_sma.n_rx),
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# # pmod 0-7 pin
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Instance("OBUF", i_I=o, o_O=pmod[0]),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]),
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Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod[2]),
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Instance("OBUF", i_I=prioity_0, o_O=pmod[3]),
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Instance("OBUF", i_I=word_bound, o_O=pmod[4]),
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Instance("OBUF", i_I=idling, o_O=pmod[5]),
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Instance("OBUF", i_I=o, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=idling, o_O=pmod_pads[5]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]),
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# Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]),
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Instance("OBUF", i_I=p0, o_O=pmod[6]),
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Instance("OBUF", i_I=p3, o_O=pmod[7]),
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Instance("OBUF", i_I=p0, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=p3, o_O=pmod_pads[7]),
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]
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self.symbol0 = CSR(9)
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self.symbol1 = CSR(9)
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