From 75407b2ff45c6aeb3aa0167dc3dd674786850b54 Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 27 Aug 2024 10:54:15 +0800 Subject: [PATCH] cxp upconn: add upconn pads & cleanup cxp upconn: cleanup --- src/gateware/cxp_upconn.py | 38 +++++++++++++++++++------------------- 1 file changed, 19 insertions(+), 19 deletions(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index f9ac57d..d18f3bf 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -8,8 +8,7 @@ from misoc.interconnect.csr import * class CXP_UpConn(Module, AutoCSR): - nfifos = 3 - def __init__(self, pads, sys_clk_freq, pmod, fifo_depth=32): + def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, fifo_depth, nfifos=3): self.clock_domains.cd_cxp_upconn = ClockDomain() self.clk_reset = CSRStorage(reset=1) self.bitrate2x_enable = CSRStorage() @@ -50,11 +49,14 @@ class CXP_UpConn(Module, AutoCSR): AsyncResetSynchronizer(self.cd_cxp_upconn, ~pll_locked | self.clk_reset.storage) ] - self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE")) + self.submodules.startup_fsm = startup_fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="WAIT_TX_ENABLE")) + self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True)) self.submodules.tx_fifos = tx_fifos = TxFIFOs(self.nfifos, fifo_depth) self.submodules.tx_idle = tx_idle = TxIdle() o = Signal() + self.specials += Instance("OBUF", i_I=o, o_O=pad), + tx_en = Signal() tx_bitcount = Signal(max=10) tx_charcount = Signal(max=4) @@ -64,24 +66,22 @@ class CXP_UpConn(Module, AutoCSR): priorities = Signal(max=self.nfifos) idling = Signal() - self.submodules.encoder = encoder = ClockDomainsRenamer("cxp_upconn")(SingleEncoder(True)) - # startup sequence - self.fsm.act("WAIT_TX_ENABLE", + startup_fsm.act("WAIT_TX_ENABLE", If(self.tx_enable.storage, NextValue(tx_idle.word_idx, 0), NextState("ENCODE_CHAR") ) ) - self.fsm.act("ENCODE_CHAR", + startup_fsm.act("ENCODE_CHAR", NextValue(tx_idle.source_ack, 1), NextValue(encoder.d, tx_idle.source_data), NextValue(encoder.k, tx_idle.source_k), NextState("LOAD_CHAR"), ) - self.fsm.act("LOAD_CHAR", + startup_fsm.act("LOAD_CHAR", NextValue(idling, 1), NextValue(tx_charcount, 0), NextValue(tx_bitcount, 0), @@ -91,7 +91,7 @@ class CXP_UpConn(Module, AutoCSR): NextState("START_TX") ) - self.fsm.act("START_TX", + startup_fsm.act("START_TX", tx_en.eq(1), If((~self.tx_enable.storage) & (tx_charcount == 3), NextState("WAIT_TX_ENABLE") @@ -183,21 +183,21 @@ class CXP_UpConn(Module, AutoCSR): ] self.specials += [ # # debug sma - # Instance("OBUF", i_I=o, o_O=pads.p_tx), - # Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pads.n_rx), + Instance("OBUF", i_I=o, o_O=debug_sma.p_tx), + Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=debug_sma.n_rx), # # pmod 0-7 pin - Instance("OBUF", i_I=o, o_O=pmod[0]), - Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod[1]), - Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod[2]), - Instance("OBUF", i_I=prioity_0, o_O=pmod[3]), - Instance("OBUF", i_I=word_bound, o_O=pmod[4]), - Instance("OBUF", i_I=idling, o_O=pmod[5]), + Instance("OBUF", i_I=o, o_O=pmod_pads[0]), + Instance("OBUF", i_I=self.cd_cxp_upconn.clk, o_O=pmod_pads[1]), + Instance("OBUF", i_I=~tx_fifos.pe.n, o_O=pmod_pads[2]), + Instance("OBUF", i_I=prioity_0, o_O=pmod_pads[3]), + Instance("OBUF", i_I=word_bound, o_O=pmod_pads[4]), + Instance("OBUF", i_I=idling, o_O=pmod_pads[5]), # Instance("OBUF", i_I=tx_fifos.source_ack[0], o_O=pmod[6]), # Instance("OBUF", i_I=tx_fifos.source_ack[2], o_O=pmod[6]), # Instance("OBUF", i_I=tx_fifos.source_ack[1], o_O=pmod[7]), - Instance("OBUF", i_I=p0, o_O=pmod[6]), - Instance("OBUF", i_I=p3, o_O=pmod[7]), + Instance("OBUF", i_I=p0, o_O=pmod_pads[6]), + Instance("OBUF", i_I=p3, o_O=pmod_pads[7]), ] self.symbol0 = CSR(9) self.symbol1 = CSR(9)