forked from M-Labs/artiq-zynq
cxp GW: use upconn layout
This commit is contained in:
parent
cb0a0358a3
commit
7285479f5b
|
@ -36,9 +36,7 @@ class UpConn_Interface(Module, AutoCSR):
|
||||||
|
|
||||||
# # #
|
# # #
|
||||||
|
|
||||||
layout = [("data", 8), ("k", 1)]
|
self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
|
||||||
|
|
||||||
self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout)
|
|
||||||
|
|
||||||
self.sync += [
|
self.sync += [
|
||||||
phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
|
phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
|
||||||
|
@ -50,7 +48,7 @@ class UpConn_Interface(Module, AutoCSR):
|
||||||
|
|
||||||
# Packet FIFOs with transmission priority
|
# Packet FIFOs with transmission priority
|
||||||
# 0: Trigger packet
|
# 0: Trigger packet
|
||||||
self.submodules.trig = trig = TX_Trigger(layout)
|
self.submodules.trig = trig = TX_Trigger()
|
||||||
self.comb += trig.source.connect(phy.sinks[0])
|
self.comb += trig.source.connect(phy.sinks[0])
|
||||||
|
|
||||||
# DEBUG: INPUT
|
# DEBUG: INPUT
|
||||||
|
@ -66,7 +64,7 @@ class UpConn_Interface(Module, AutoCSR):
|
||||||
|
|
||||||
|
|
||||||
# 1: IO acknowledgment for trigger packet
|
# 1: IO acknowledgment for trigger packet
|
||||||
self.submodules.trig_ack = trig_ack = Trigger_ACK(layout)
|
self.submodules.trig_ack = trig_ack = Trigger_ACK()
|
||||||
self.comb += trig_ack.source.connect(phy.sinks[1])
|
self.comb += trig_ack.source.connect(phy.sinks[1])
|
||||||
|
|
||||||
# DEBUG: INPUT
|
# DEBUG: INPUT
|
||||||
|
@ -76,11 +74,11 @@ class UpConn_Interface(Module, AutoCSR):
|
||||||
|
|
||||||
# 2: All other packets
|
# 2: All other packets
|
||||||
# Control is not timing dependent, all the link layer is done in firmware
|
# Control is not timing dependent, all the link layer is done in firmware
|
||||||
self.submodules.command = command = TX_Command_Packet(layout)
|
self.submodules.command = command = TX_Command_Packet()
|
||||||
self.submodules.testseq = testseq = TX_Test_Packet(layout)
|
self.submodules.testseq = testseq = TX_Test_Packet()
|
||||||
|
|
||||||
|
|
||||||
self.submodules.mux = mux = stream.Multiplexer(layout, 2)
|
self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2)
|
||||||
|
|
||||||
self.comb += [
|
self.comb += [
|
||||||
command.source.connect(mux.sink0),
|
command.source.connect(mux.sink0),
|
||||||
|
|
Loading…
Reference in New Issue