From 7285479f5b21f2a240f975fb144728a52881ae95 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 12 Sep 2024 13:04:58 +0800 Subject: [PATCH] cxp GW: use upconn layout --- src/gateware/cxp.py | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/gateware/cxp.py b/src/gateware/cxp.py index 534a66e..cd23c54 100644 --- a/src/gateware/cxp.py +++ b/src/gateware/cxp.py @@ -36,9 +36,7 @@ class UpConn_Interface(Module, AutoCSR): # # # - layout = [("data", 8), ("k", 1)] - - self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads, layout) + self.submodules.phy = phy = CXP_UpConn_PHY(upconn_pads, sys_clk_freq, debug_sma, pmod_pads) self.sync += [ phy.bitrate2x_enable.eq(self.bitrate2x_enable.storage), @@ -50,7 +48,7 @@ class UpConn_Interface(Module, AutoCSR): # Packet FIFOs with transmission priority # 0: Trigger packet - self.submodules.trig = trig = TX_Trigger(layout) + self.submodules.trig = trig = TX_Trigger() self.comb += trig.source.connect(phy.sinks[0]) # DEBUG: INPUT @@ -66,7 +64,7 @@ class UpConn_Interface(Module, AutoCSR): # 1: IO acknowledgment for trigger packet - self.submodules.trig_ack = trig_ack = Trigger_ACK(layout) + self.submodules.trig_ack = trig_ack = Trigger_ACK() self.comb += trig_ack.source.connect(phy.sinks[1]) # DEBUG: INPUT @@ -76,11 +74,11 @@ class UpConn_Interface(Module, AutoCSR): # 2: All other packets # Control is not timing dependent, all the link layer is done in firmware - self.submodules.command = command = TX_Command_Packet(layout) - self.submodules.testseq = testseq = TX_Test_Packet(layout) + self.submodules.command = command = TX_Command_Packet() + self.submodules.testseq = testseq = TX_Test_Packet() - self.submodules.mux = mux = stream.Multiplexer(layout, 2) + self.submodules.mux = mux = stream.Multiplexer(upconn_layout, 2) self.comb += [ command.source.connect(mux.sink0),