From 6636339701dc11545280bc58c41268e5529cda0a Mon Sep 17 00:00:00 2001 From: morgan Date: Tue, 18 Jun 2024 16:40:40 +0800 Subject: [PATCH] cxp upconn: refactor serial fsm as sync logic --- src/gateware/cxp_upconn.py | 42 +++++++++++--------------------------- 1 file changed, 12 insertions(+), 30 deletions(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index 1046ca1..88b7171 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -58,37 +58,8 @@ class CXP_UpConn(Module, AutoCSR): o = Signal() bits = Signal(max=tx_width) tx_reg = Signal(tx_width) - busy = Signal() - self.submodules.fsm = ClockDomainsRenamer("cxp_upconn")(FSM(reset_state="IDLE")) self.submodules.encoder = SingleEncoder(True) - - self.fsm.act("IDLE", - NextValue(o, 0), - If(self.stb.storage, - NextValue(bits, 0), - NextValue(tx_reg, self.encoder.output), - NextValue(self.tx_reg.status, self.encoder.output), - NextValue(self.encoder.disp_in, self.encoder.disp_out), - NextState("WRITE") - ) - ) - self.fsm.act("WRITE", - NextValue(o, tx_reg[0]), - NextValue(tx_reg, Cat(tx_reg[1:], 0)), - If(bits == tx_width - 1, - If(self.stb.storage, - NextValue(bits, 0), - NextValue(tx_reg, self.encoder.output), - NextValue(self.tx_reg.status, self.encoder.output), - NextValue(self.encoder.disp_in, self.encoder.disp_out), - ).Else( - NextState("IDLE"), - ), - ).Else( - NextValue(bits, bits + 1) - ) - ) self.comb += [ self.encoder.d.eq(self.data.storage), @@ -97,9 +68,20 @@ class CXP_UpConn(Module, AutoCSR): self.sync.cxp_upconn +=[ self.encoded.status.eq(self.encoder.output), + If(self.stb.storage, + o.eq(tx_reg[0]), + tx_reg.eq(Cat(tx_reg[1:], 0)) + ), + If(bits != tx_width - 1, + bits.eq(bits + 1), + ).Elif(self.stb.storage, + bits.eq(0), + tx_reg.eq(self.encoder.output), + self.tx_reg.status.eq(self.encoder.output), + self.encoder.disp_in.eq(self.encoder.disp_out), + ) ] - self.comb += busy.eq(~self.fsm.ongoing("IDLE")) # DEBUG: remove pads self.specials += [ Instance("OBUF", i_I=o, o_O=pads.p_tx),