forked from M-Labs/artiq-zynq
cxp GW: add rx debug packet loopback
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@ -23,6 +23,17 @@ class DownConn_Interface(Module, AutoCSR):
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self.submodules.phy = phy = CXP_DownConn_PHY(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
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self.gtxs = phy.gtxs
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# TODO add mux here and fifos
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# decoder -> priorities mux(normal packet vs trigger ack) -> data packet mux (control ack, data stream, heartbeat, testmode, (optional Genlcam event))
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self.submodules.debug_src = debug_src = TX_Command_Packet()
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self.submodules.conv = conv = stream.StrideConverter(upconn_layout, downconn_layout, reverse=True)
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self.submodules.debug_out = debug_out = RX_Debug_Buffer()
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rx_pipeline = [debug_src, conv, debug_out]
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for s, d in zip(rx_pipeline, rx_pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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class UpConn_Interface(Module, AutoCSR):
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