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artiq-zynq
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master wrpll: remove nested mmcm module

This commit is contained in:
morgan 2024-02-29 16:25:03 +08:00
parent 7300ecce25
commit 5aade6abb2
1 changed files with 94 additions and 99 deletions
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11
src/libboard_artiq/src/si549.rs
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@ -552,10 +552,6 @@ pub mod wrpll {
pub mod sma_pll {
use super::*;
mod mmcm {
use super::*;
pub struct MmcmSetting {
pub clkout0_reg1: u16, //0x08
pub clkout0_reg2: u16, //0x09
@ -613,7 +609,7 @@ pub mod sma_pll {
unsafe { csr::sma_pll::drp_ready_read() == 1 }
}
pub fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
fn read(timer: &mut GlobalTimer, address: u8) -> u16 {
set_addr(address);
set_enable(true);
// Set DADDR on the MMCM and assert DEN for one clock cycle
@ -627,7 +623,7 @@ pub mod sma_pll {
get_data()
}
pub fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
fn write(timer: &mut GlobalTimer, address: u8, value: u16) {
set_addr(address);
set_data(value);
set_write_enable(true);
@ -643,7 +639,7 @@ pub mod sma_pll {
}
}
pub fn reset(rst: bool) {
fn reset(rst: bool) {
unsafe {
let val = if rst { 1 } else { 0 };
csr::sma_pll::mmcm_reset_write(val)
@ -677,7 +673,6 @@ pub mod sma_pll {
}
Ok(())
}
}
pub fn setup(timer: &mut GlobalTimer) {
for addr in 7..12 {