From 5aade6abb295b0b4efc731b1e4d4e5727d6cf77e Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 29 Feb 2024 16:25:03 +0800 Subject: [PATCH] master wrpll: remove nested mmcm module --- src/libboard_artiq/src/si549.rs | 193 ++++++++++++++++---------------- 1 file changed, 94 insertions(+), 99 deletions(-) diff --git a/src/libboard_artiq/src/si549.rs b/src/libboard_artiq/src/si549.rs index 5c64597..72f0223 100644 --- a/src/libboard_artiq/src/si549.rs +++ b/src/libboard_artiq/src/si549.rs @@ -552,131 +552,126 @@ pub mod wrpll { pub mod sma_pll { use super::*; - mod mmcm { + pub struct MmcmSetting { + pub clkout0_reg1: u16, //0x08 + pub clkout0_reg2: u16, //0x09 + pub clkfbout_reg1: u16, //0x14 + pub clkfbout_reg2: u16, //0x15 + pub div_reg: u16, //0x16 + pub lock_reg1: u16, //0x18 + pub lock_reg2: u16, //0x19 + pub lock_reg3: u16, //0x1A + pub power_reg: u16, //0x28 + pub filt_reg1: u16, //0x4E + pub filt_reg2: u16, //0x4F + } - use super::*; - - pub struct MmcmSetting { - pub clkout0_reg1: u16, //0x08 - pub clkout0_reg2: u16, //0x09 - pub clkfbout_reg1: u16, //0x14 - pub clkfbout_reg2: u16, //0x15 - pub div_reg: u16, //0x16 - pub lock_reg1: u16, //0x18 - pub lock_reg2: u16, //0x19 - pub lock_reg3: u16, //0x1A - pub power_reg: u16, //0x28 - pub filt_reg1: u16, //0x4E - pub filt_reg2: u16, //0x4F + fn one_clock_cycle(timer: &mut GlobalTimer) { + unsafe { + csr::sma_pll::drp_clk_write(1); + timer.delay_us(1); + csr::sma_pll::drp_clk_write(0); + timer.delay_us(1); } + } - fn one_clock_cycle(timer: &mut GlobalTimer) { - unsafe { - csr::sma_pll::drp_clk_write(1); - timer.delay_us(1); - csr::sma_pll::drp_clk_write(0); - timer.delay_us(1); - } + fn set_addr(address: u8) { + unsafe { + csr::sma_pll::drp_addr_write(address); } + } - fn set_addr(address: u8) { - unsafe { - csr::sma_pll::drp_addr_write(address); - } + fn set_data(value: u16) { + unsafe { + csr::sma_pll::drp_in_write(value); } + } - fn set_data(value: u16) { - unsafe { - csr::sma_pll::drp_in_write(value); - } + fn set_enable(en: bool) { + unsafe { + let val = if en { 1 } else { 0 }; + csr::sma_pll::drp_en_write(val); } + } - fn set_enable(en: bool) { - unsafe { - let val = if en { 1 } else { 0 }; - csr::sma_pll::drp_en_write(val); - } + fn set_write_enable(en: bool) { + unsafe { + let val = if en { 1 } else { 0 }; + csr::sma_pll::drp_w_en_write(val); } + } - fn set_write_enable(en: bool) { - unsafe { - let val = if en { 1 } else { 0 }; - csr::sma_pll::drp_w_en_write(val); - } - } + fn get_data() -> u16 { + unsafe { csr::sma_pll::drp_out_read() } + } - fn get_data() -> u16 { - unsafe { csr::sma_pll::drp_out_read() } - } + fn drp_ready() -> bool { + unsafe { csr::sma_pll::drp_ready_read() == 1 } + } - fn drp_ready() -> bool { - unsafe { csr::sma_pll::drp_ready_read() == 1 } - } + fn read(timer: &mut GlobalTimer, address: u8) -> u16 { + set_addr(address); + set_enable(true); + // Set DADDR on the MMCM and assert DEN for one clock cycle + one_clock_cycle(timer); - pub fn read(timer: &mut GlobalTimer, address: u8) -> u16 { - set_addr(address); - set_enable(true); - // Set DADDR on the MMCM and assert DEN for one clock cycle + set_enable(false); + while !drp_ready() { + // keep the clock signal until data is ready one_clock_cycle(timer); - - set_enable(false); - while !drp_ready() { - // keep the clock signal until data is ready - one_clock_cycle(timer); - } - get_data() } + get_data() + } - pub fn write(timer: &mut GlobalTimer, address: u8, value: u16) { - set_addr(address); - set_data(value); - set_write_enable(true); - set_enable(true); - // Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle + fn write(timer: &mut GlobalTimer, address: u8, value: u16) { + set_addr(address); + set_data(value); + set_write_enable(true); + set_enable(true); + // Set DADDR, DI on the MMCM and assert DWE, DEN for one clock cycle + one_clock_cycle(timer); + + set_write_enable(false); + set_enable(false); + while !drp_ready() { + // keep the clock signal until write is finished one_clock_cycle(timer); - - set_write_enable(false); - set_enable(false); - while !drp_ready() { - // keep the clock signal until write is finished - one_clock_cycle(timer); - } } + } - pub fn reset(rst: bool) { - unsafe { - let val = if rst { 1 } else { 0 }; - csr::sma_pll::mmcm_reset_write(val) - } + fn reset(rst: bool) { + unsafe { + let val = if rst { 1 } else { 0 }; + csr::sma_pll::mmcm_reset_write(val) } + } - pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting) -> Result<(), &'static str> { - // Based on "DRP State Machine" from XAPP888 + pub fn setup(timer: &mut GlobalTimer, settings: MmcmSetting) -> Result<(), &'static str> { + // Based on "DRP State Machine" from XAPP888 - // hold reset HIGH during mmcm config - reset(true); - write(timer, 0x08, settings.clkout0_reg1); - write(timer, 0x09, settings.clkout0_reg2); - write(timer, 0x14, settings.clkfbout_reg1); - write(timer, 0x15, settings.clkfbout_reg2); - write(timer, 0x16, settings.div_reg); - write(timer, 0x18, settings.lock_reg1); - write(timer, 0x19, settings.lock_reg2); - write(timer, 0x1A, settings.lock_reg3); - write(timer, 0x28, settings.power_reg); - write(timer, 0x4E, settings.filt_reg1); - write(timer, 0x4F, settings.filt_reg2); - reset(false); + // hold reset HIGH during mmcm config + reset(true); + write(timer, 0x08, settings.clkout0_reg1); + write(timer, 0x09, settings.clkout0_reg2); + write(timer, 0x14, settings.clkfbout_reg1); + write(timer, 0x15, settings.clkfbout_reg2); + write(timer, 0x16, settings.div_reg); + write(timer, 0x18, settings.lock_reg1); + write(timer, 0x19, settings.lock_reg2); + write(timer, 0x1A, settings.lock_reg3); + write(timer, 0x28, settings.power_reg); + write(timer, 0x4E, settings.filt_reg1); + write(timer, 0x4F, settings.filt_reg2); + reset(false); - // wait for the mmcm to lock - timer.delay_us(100); + // wait for the mmcm to lock + timer.delay_us(100); - let locked = unsafe { csr::sma_pll::mmcm_locked_read() == 1 }; - if !locked { - return Err("failed to generate 125Mhz ref clock from SMA CLKIN"); - } - Ok(()) + let locked = unsafe { csr::sma_pll::mmcm_locked_read() == 1 }; + if !locked { + return Err("failed to generate 125Mhz ref clock from SMA CLKIN"); } + Ok(()) } pub fn setup(timer: &mut GlobalTimer) {