forked from M-Labs/artiq-zynq
cxp: connect tx command to PHY
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@ -125,41 +125,28 @@ class UpConn_Interface(Module, AutoCSR):
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# tags implementation is on firmware
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self.submodules.command = command = TX_Command_Packet(layout)
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self.comb += command.source.connect(upconn_phy.tx_fifos.sink[2])
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# DEBUG: OUTPUT
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self.submodules.command_out = command_out = stream.SyncFIFO(layout, 64)
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self.comb += command.source.connect(command_out.sink)
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# self.submodules.command_out = command_out = stream.SyncFIFO(layout, 64)
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# self.comb += command.source.connect(command_out.sink)
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self.command_inc = CSR()
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self.command_dout_pak = CSRStatus(8)
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self.command_kout_pak = CSRStatus()
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self.command_dout_valid = CSRStatus()
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# self.command_inc = CSR()
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# self.command_dout_pak = CSRStatus(8)
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# self.command_kout_pak = CSRStatus()
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# self.command_dout_valid = CSRStatus()
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self.sync += [
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# output
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command_out.source.ack.eq(self.command_inc.re),
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self.command_dout_pak.status.eq(command_out.source.data),
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self.command_kout_pak.status.eq(command_out.source.k),
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self.command_dout_valid.status.eq(command_out.source.stb),
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]
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# self.sync += [
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# # output
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# command_out.source.ack.eq(self.command_inc.re),
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# self.command_dout_pak.status.eq(command_out.source.data),
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# self.command_kout_pak.status.eq(command_out.source.k),
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# self.command_dout_valid.status.eq(command_out.source.stb),
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# ]
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self.specials += [
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# pmod 0-7 pin
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Instance("OBUF", i_I=command.pak_wrp.sink.stb, o_O=pmod_pads[0]),
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Instance("OBUF", i_I=command.pak_wrp.sink.ack, o_O=pmod_pads[1]),
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Instance("OBUF", i_I=command.pak_wrp.source.stb, o_O=pmod_pads[2]),
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Instance("OBUF", i_I=command.pak_wrp.source.ack, o_O=pmod_pads[3]),
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Instance("OBUF", i_I=command_out.sink.stb, o_O=pmod_pads[4]),
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Instance("OBUF", i_I=command_out.sink.ack, o_O=pmod_pads[5]),
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Instance("OBUF", i_I=command_out.source.stb, o_O=pmod_pads[6]),
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Instance("OBUF", i_I=command_out.source.ack, o_O=pmod_pads[7]),
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]
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self.symbol2 = CSR(9)
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self.sync += [
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upconn_phy.tx_fifos.sink[2].stb.eq(self.symbol2.re),
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upconn_phy.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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]
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# self.symbol2 = CSR(9)
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# self.sync += [
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# upconn_phy.tx_fifos.sink[2].stb.eq(self.symbol2.re),
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# upconn_phy.tx_fifos.sink[2].data.eq(self.symbol2.r[:8]),
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# upconn_phy.tx_fifos.sink[2].k.eq(self.symbol2.r[8]),
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# ]
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