forked from M-Labs/artiq-zynq
cxp upconn: rename to phy
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0b2f201c09
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@ -219,7 +219,7 @@ class TxFIFOs(Module):
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self.submodules.pe = PriorityEncoder(nfifos)
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self.comb += self.pe.i.eq(self.source_stb)
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class CXP_UpConn(Module):
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class CXP_UpConn_PHY(Module):
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def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
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self.bitrate2x_enable = Signal()
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self.clk_reset = Signal()
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