forked from M-Labs/artiq-zynq
cxp upconn fw: add clk reset & busy csr
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parent
535b79cfd4
commit
0b2f201c09
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@ -57,7 +57,9 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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let mut arr: [u16; LEN] = [0; LEN];
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unsafe {
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csr::cxp::upconn_clk_reset_write(1);
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// csr::cxp::upconn_bitrate2x_enable_write(1);
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csr::cxp::upconn_clk_reset_write(0);
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loop {
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// TODO: verify the char & word boundary thingy
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@ -74,6 +76,9 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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for i in 0..LEN {
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arr[i] = get_encoded();
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// if csr::cxp::upconn_tx_busy_read() == 0 {
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// break;
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// };
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}
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let mut last_encoded: u16 = 0;
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for i in 0..LEN {
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@ -89,7 +94,7 @@ pub fn tx_test(timer: &mut GlobalTimer) {
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println!("D04.4")
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}
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0b0011111010 | 0b1100000101 => {
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println!("K28.5 start idling....")
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println!("K28.5 start idling...")
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}
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0b0011111001 | 0b1100000110 => {
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println!("K28.1 idling...")
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