forked from M-Labs/artiq-zynq
cxp upconn: rename to phy
This commit is contained in:
parent
0b2f201c09
commit
47d38fce32
|
@ -219,7 +219,7 @@ class TxFIFOs(Module):
|
||||||
self.submodules.pe = PriorityEncoder(nfifos)
|
self.submodules.pe = PriorityEncoder(nfifos)
|
||||||
self.comb += self.pe.i.eq(self.source_stb)
|
self.comb += self.pe.i.eq(self.source_stb)
|
||||||
|
|
||||||
class CXP_UpConn(Module):
|
class CXP_UpConn_PHY(Module):
|
||||||
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
|
def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads, cxp_phy_layout, fifo_depth, nfifos=3):
|
||||||
self.bitrate2x_enable = Signal()
|
self.bitrate2x_enable = Signal()
|
||||||
self.clk_reset = Signal()
|
self.clk_reset = Signal()
|
||||||
|
|
Loading…
Reference in New Issue