forked from M-Labs/artiq-zynq
cxp downconn fw: add qpll linerate change
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parent
5a40422f1d
commit
4436dc930e
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@ -131,13 +131,14 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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csr::cxp::downconn_tx_start_init_write(1);
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csr::cxp::downconn_tx_start_init_write(1);
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csr::cxp::downconn_rx_start_init_write(1);
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csr::cxp::downconn_rx_start_init_write(1);
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info!("waiting for tx setup...");
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info!("waiting for tx & rx setup...");
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timer.delay_us(50_000);
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timer.delay_us(50_000);
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info!(
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info!(
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"tx_phaligndone = {} | rx_phaligndone = {}",
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"tx_phaligndone = {} | rx_phaligndone = {}",
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csr::cxp::downconn_txinit_phaligndone_read(),
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csr::cxp::downconn_txinit_phaligndone_read(),
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csr::cxp::downconn_rxinit_phaligndone_read(),
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csr::cxp::downconn_rxinit_phaligndone_read(),
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);
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);
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println!("==============================================================================");
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}
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}
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change_linerate(timer, speed);
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change_linerate(timer, speed);
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@ -146,9 +147,11 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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}
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}
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pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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// TODO: switch QPLL divider for RXUSRCLK
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// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
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let settings = txusrclk::get_txusrclk_config(speed);
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txusrclk::setup(timer, settings);
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// TODO: set TX/RXDIV via TX/RXRATE
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// TODO: set TX/RX DIVIDER via TX/RXRATE
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change_qpll_settings(speed);
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change_qpll_settings(speed);
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unsafe {
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unsafe {
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@ -158,13 +161,9 @@ pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) {
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info!("QPLL locked");
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info!("QPLL locked");
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}
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}
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// DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20
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let settings = txusrclk::get_txusrclk_config(speed);
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txusrclk::setup(timer, settings);
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// reset tx&rx for phase alignment
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// reset tx&rx for phase alignment
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unsafe {
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unsafe {
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// csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
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csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset
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csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm
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csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm
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}
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}
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}
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}
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