From 4436dc930ef93129cea1cd2af7a3c1115413442a Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 1 Aug 2024 12:33:22 +0800 Subject: [PATCH] cxp downconn fw: add qpll linerate change --- src/libboard_artiq/src/cxp_downconn.rs | 15 +++++++-------- 1 file changed, 7 insertions(+), 8 deletions(-) diff --git a/src/libboard_artiq/src/cxp_downconn.rs b/src/libboard_artiq/src/cxp_downconn.rs index fb5f52f..bb187d5 100644 --- a/src/libboard_artiq/src/cxp_downconn.rs +++ b/src/libboard_artiq/src/cxp_downconn.rs @@ -131,13 +131,14 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) { csr::cxp::downconn_tx_start_init_write(1); csr::cxp::downconn_rx_start_init_write(1); - info!("waiting for tx setup..."); + info!("waiting for tx & rx setup..."); timer.delay_us(50_000); info!( "tx_phaligndone = {} | rx_phaligndone = {}", csr::cxp::downconn_txinit_phaligndone_read(), csr::cxp::downconn_rxinit_phaligndone_read(), ); + println!("=============================================================================="); } change_linerate(timer, speed); @@ -146,9 +147,11 @@ pub fn setup(timer: &mut GlobalTimer, speed: CXP_SPEED) { } pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) { - // TODO: switch QPLL divider for RXUSRCLK + // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20 + let settings = txusrclk::get_txusrclk_config(speed); + txusrclk::setup(timer, settings); - // TODO: set TX/RXDIV via TX/RXRATE + // TODO: set TX/RX DIVIDER via TX/RXRATE change_qpll_settings(speed); unsafe { @@ -158,13 +161,9 @@ pub fn change_linerate(timer: &mut GlobalTimer, speed: CXP_SPEED) { info!("QPLL locked"); } - // DEBUG: DRP pll for TXUSRCLK = freq(linerate)/20 - let settings = txusrclk::get_txusrclk_config(speed); - txusrclk::setup(timer, settings); - // reset tx&rx for phase alignment unsafe { - // csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset + csr::cxp::downconn_tx_restart_write(1); // <--- NOTE: changing TXRATE will do reset automatically, no need to manually reset csr::cxp::downconn_rx_restart_write(1); // <--- NOTE: this doesn't do anything atm } }