morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

master wrpll: default vco to 1.25Ghz

This commit is contained in:
morgan 2024-02-29 17:43:19 +08:00
parent 963a4822c4
commit 30392c9ca8
1 changed files with 4 additions and 6 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gateware/wrpll.py
View File

@ -160,14 +160,12 @@ class SMAFrequencyMultiplier(Module, AutoCSR):
i_CLKIN1=ClockSignal("sys"),
i_CLKINSEL=1, # 1=CLKIN1 0=CLKIN2
# VCO @ 1Ghz
p_CLKFBOUT_MULT_F=8.0,
# p_CLKFBOUT_MULT = 1.0, # M = p_CLKFBOUT_MULT_F/p_CLKFBOUT_MULT
p_DIVCLK_DIVIDE=1,
# VCO @ 1.25Ghz
p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
i_CLKFBIN=mmcm_fb_clk, o_CLKFBOUT=mmcm_fb_clk,
# 62.5MHz
p_CLKOUT0_DIVIDE_F=16, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
# 125Mhz for WRPLL
p_CLKOUT0_DIVIDE_F=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
# Dynamic Reconfiguration Port
i_DADDR = self.mmcm_daddr.storage,