From 30392c9ca8f0ce54c1b990648c3ef3f29c8d99c1 Mon Sep 17 00:00:00 2001
From: morgan <mc@m-labs.hk>
Date: Thu, 29 Feb 2024 17:43:19 +0800
Subject: [PATCH] master wrpll: default vco to 1.25Ghz

---
 src/gateware/wrpll.py | 10 ++++------
 1 file changed, 4 insertions(+), 6 deletions(-)

diff --git a/src/gateware/wrpll.py b/src/gateware/wrpll.py
index ccc3924..fb44047 100644
--- a/src/gateware/wrpll.py
+++ b/src/gateware/wrpll.py
@@ -160,14 +160,12 @@ class SMAFrequencyMultiplier(Module, AutoCSR):
                 i_CLKIN1=ClockSignal("sys"),
                 i_CLKINSEL=1,  # 1=CLKIN1 0=CLKIN2
 
-                # VCO @ 1Ghz
-                p_CLKFBOUT_MULT_F=8.0,
-                # p_CLKFBOUT_MULT = 1.0, # M = p_CLKFBOUT_MULT_F/p_CLKFBOUT_MULT
-                p_DIVCLK_DIVIDE=1,
+                # VCO @ 1.25Ghz
+                p_CLKFBOUT_MULT_F=10, p_DIVCLK_DIVIDE=1,
                 i_CLKFBIN=mmcm_fb_clk, o_CLKFBOUT=mmcm_fb_clk, 
 
-                # 62.5MHz
-                p_CLKOUT0_DIVIDE_F=16, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
+                # 125Mhz for WRPLL
+                p_CLKOUT0_DIVIDE_F=10, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=ref_clk,
 
                 # Dynamic Reconfiguration Port
                 i_DADDR = self.mmcm_daddr.storage,