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zc706 GW: remove tx 312.5MHz limit

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morgan 2025-01-16 10:50:12 +08:00
parent 9251946952
commit 1ff9205cc8
1 changed files with 1 additions and 2 deletions
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src/gateware/zc706.py
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@ -748,10 +748,9 @@ class CXP_FMC():
# zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns) # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
# pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
rx = cxp_phys.phys[0].rx rx = cxp_phys.phys[0].rx
platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2) platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
# constraint the CLK path # constraint the CLK path
platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk) platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_rx.clk)
# FIXME remove this placeholder RTIO channel # FIXME remove this placeholder RTIO channel
# There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor) # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)