From 1ff9205cc8a449ab32f435555b0162f99d5e65df Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 16 Jan 2025 10:50:12 +0800 Subject: [PATCH] zc706 GW: remove tx 312.5MHz limit --- src/gateware/zc706.py | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/gateware/zc706.py b/src/gateware/zc706.py index 64ce081..81d6ac6 100755 --- a/src/gateware/zc706.py +++ b/src/gateware/zc706.py @@ -748,10 +748,9 @@ class CXP_FMC(): # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns) # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met rx = cxp_phys.phys[0].rx - platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2) platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2) # constraint the CLK path - platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk) + platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_rx.clk) # FIXME remove this placeholder RTIO channel # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)