morgan
/
artiq-zynq
forked from M-Labs/artiq-zynq
1
0
Fork 0
Code Pull Requests Activity

upconn GW: link all phy ctrl tgt 

upconn GW: rename csr

upconn GW: add serdes ouput
This commit is contained in:
morgan 2024-10-17 15:46:41 +08:00
parent d73cd459f0
commit 11b3842a7f
1 changed files with 13 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

14
src/gateware/cxp_upconn.py
View File

@ -180,7 +180,7 @@ class Transmitter(Module, AutoCSR):
self.specials += [
# # debug sma
# Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx),
# Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx),
Instance("OBUF", i_I=serdes.o, o_O=debug_sma.n_rx),
@ -205,8 +205,20 @@ class Transmitter(Module, AutoCSR):
class CXP_UpConn_PHYS(Module, AutoCSR):
def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
self.clk_reset = CSR()
self.bitrate2x_enable = CSRStorage()
self.tx_enable = CSRStorage()
# # #
self.tx_phys = []
for i, pad in enumerate(pads):
tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
self.tx_phys.append(tx)
setattr(self.submodules, "tx"+str(i), tx)
self.sync += [
tx.clk_reset.eq(self.clk_reset.re),
tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
tx.tx_enable.eq(self.tx_enable.storage),
]