From 11b3842a7fa26dc9d41c4613d1f6b44ca377fe88 Mon Sep 17 00:00:00 2001 From: morgan Date: Thu, 17 Oct 2024 15:46:41 +0800 Subject: [PATCH] upconn GW: link all phy ctrl tgt upconn GW: rename csr upconn GW: add serdes ouput --- src/gateware/cxp_upconn.py | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/src/gateware/cxp_upconn.py b/src/gateware/cxp_upconn.py index 0177818..e4c2c26 100644 --- a/src/gateware/cxp_upconn.py +++ b/src/gateware/cxp_upconn.py @@ -180,7 +180,7 @@ class Transmitter(Module, AutoCSR): self.specials += [ # # debug sma # Instance("OBUF", i_I=serdes.o, o_O=debug_sma.p_tx), - # Instance("OBUF", i_I=cg.clk_10x, o_O=debug_sma.n_rx), + Instance("OBUF", i_I=serdes.o, o_O=debug_sma.n_rx), @@ -205,8 +205,20 @@ class Transmitter(Module, AutoCSR): class CXP_UpConn_PHYS(Module, AutoCSR): def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads): + self.clk_reset = CSR() + self.bitrate2x_enable = CSRStorage() + self.tx_enable = CSRStorage() + + # # # + + self.tx_phys = [] for i, pad in enumerate(pads): tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads) self.tx_phys.append(tx) setattr(self.submodules, "tx"+str(i), tx) + self.sync += [ + tx.clk_reset.eq(self.clk_reset.re), + tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage), + tx.tx_enable.eq(self.tx_enable.storage), + ]