forked from M-Labs/artiq-zynq
394 lines
12 KiB
Python
394 lines
12 KiB
Python
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
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from src.gateware.cxp_pipeline import *
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class EOP_Marker(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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last_stb = Signal()
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self.sync += [
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If((~self.source.stb | self.source.ack),
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self.source.stb.eq(self.sink.stb),
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self.source.payload.eq(self.sink.payload),
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),
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last_stb.eq(self.sink.stb),
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]
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self.comb += [
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self.sink.ack.eq(~self.source.stb | self.source.ack),
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self.source.eop.eq(~self.sink.stb & last_stb),
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]
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class Stream_MetaData_Extractor(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# GOAL:
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# 0) accept four sinks??
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# 1) decode SPH, SPT
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# 2) decode Image header, line break
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# 3) verify the crc before phrasing image data downstream
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# HOW??
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# combine streams?
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# phrase linedata to sys CD
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# check stream data tag
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# only need to support mono16 for now
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self.stream_id = Signal(char_width)
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self.pak_tag = Signal(char_width)
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self.stream_pak_size = Signal(char_width * 2)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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fsm.act(
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"WAIT_HEADER",
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NextValue(self.stream_id, self.stream_id.reset),
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NextValue(self.pak_tag, self.pak_tag.reset),
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NextValue(self.stream_pak_size, self.stream_pak_size.reset),
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_id, self.sink.dchar),
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NextState("GET_PAK_TAG"),
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),
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)
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fsm.act(
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"GET_PAK_TAG",
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If(
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self.sink.stb,
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self.sink.ack.eq(1),
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NextValue(self.pak_tag, self.sink.dchar),
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NextState("GET_PAK_SIZE_0"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_0",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[8:], self.sink.dchar),
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NextState("GET_PAK_SIZE_1"),
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),
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)
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fsm.act(
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"GET_PAK_SIZE_1",
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self.sink.ack.eq(1),
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If(
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self.sink.stb,
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NextValue(self.stream_pak_size[:8], self.sink.dchar),
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NextState("STORE_BUFFER"),
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),
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)
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fsm.act(
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"STORE_BUFFER",
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self.sink.connect(self.source),
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# both serve the same function but using the pak size I can remove eop injecter and save 1 cycle
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If(self.sink.stb,
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NextValue(self.stream_pak_size, self.stream_pak_size - 1),
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If(self.stream_pak_size == 1,
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NextState("WAIT_HEADER"),
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)
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),
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# If((self.sink.stb & self.sink.eop),
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# NextState("WAIT_HEADER"),
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# )
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)
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class Frame_Decoder(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: decode Image header, line break
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class Pixel_Decoder(Module):
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def __init__(self, pixel_format="mono16"):
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assert pixel_format == "mono16"
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self.sink = stream.Endpoint(word_layout_dchar)
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self.source = stream.Endpoint(word_layout_dchar)
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# # #
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# TODO: support mono16 for now?
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class Streams_Dispatcher(Module):
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def __init__(self, downconns):
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n_downconn = len(downconns)
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, n_downconn)
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for i, c in enumerate(downconns):
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# if i == 0:
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self.comb += [
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# no backpressure
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c.source.ack.eq(1),
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c.source.connect(getattr(mux, "sink"+str(i)))
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]
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self.source = stream.Endpoint(word_layout_dchar)
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self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
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# TODO: add different downstream
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# stream_id = Signal()
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# case = dict((i, mux.source.connect(b.sink)) for i, b in enumerate(buffers))
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fsm.act(
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"WAIT_HEADER",
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mux.source.connect(self.source),
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If(mux.source.eop,
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NextState("SWITCH_CONN"),
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),
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)
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read_mask = Signal(max=n_downconn)
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self.comb += mux.sel.eq(read_mask)
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fsm.act(
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"SWITCH_CONN",
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If(read_mask == n_downconn - 1,
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NextValue(read_mask, read_mask.reset),
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).Else(
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NextValue(read_mask, read_mask + 1),
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),
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NextState("WAIT_HEADER"),
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)
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def reverse_bytes(s):
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assert len(s) % 8 == 0
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char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
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return Cat(char[::-1])
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@ResetInserter()
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@CEInserter()
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class CXPCRC32(Module):
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# Section 9.2.2.2 (CXP-001-2021)
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width = 32
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polynom = 0x04C11DB7
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seed = 2**width - 1
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check = 0x00000000
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def __init__(self, data_width):
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self.data = Signal(data_width)
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self.value = Signal(self.width)
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self.error = Signal()
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# # #
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self.submodules.engine = LiteEthMACCRCEngine(
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data_width, self.width, self.polynom
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)
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reg = Signal(self.width, reset=self.seed)
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self.sync += reg.eq(self.engine.next)
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self.comb += [
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# the CRC Engine use Big Endian, need to reverse the bytes
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self.engine.data.eq(reverse_bytes(self.data)),
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self.engine.last.eq(reg),
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self.value.eq(reverse_bytes(reg[::-1])),
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self.error.eq(reg != self.check),
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]
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class CXPCRC32Inserter(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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crc.reset.eq(1),
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("COPY"),
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)
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)
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fsm.act("COPY",
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crc.ce.eq(self.sink.stb & self.source.ack),
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crc.data.eq(self.sink.data),
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT"),
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)
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)
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fsm.act("INSERT",
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self.source.stb.eq(1),
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self.source.eop.eq(1),
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self.source.data.eq(crc.value),
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If(self.source.ack, NextState("IDLE"))
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)
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class StreamPacket_Wrapper(Module):
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def __init__(self):
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self.sink = stream.Endpoint(word_layout)
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self.source = stream.Endpoint(word_layout)
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# # #
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self.submodules.fsm = fsm = FSM(reset_state="IDLE")
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fsm.act("IDLE",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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self.sink.ack.eq(0),
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NextState("INSERT_HEADER_0"),
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)
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)
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fsm.act("INSERT_HEADER_0",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_start"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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If(self.source.ack, NextState("INSERT_HEADER_1")),
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)
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fsm.act("INSERT_HEADER_1",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(C(0x01, char_width), 4)),
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self.source.k.eq(Replicate(0, 4)),
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If(self.source.ack, NextState("COPY")),
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)
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fsm.act("COPY",
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self.sink.connect(self.source),
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self.source.eop.eq(0),
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If(self.sink.stb & self.sink.eop & self.source.ack,
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NextState("INSERT_FOOTER"),
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),
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)
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fsm.act("INSERT_FOOTER",
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self.sink.ack.eq(0),
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self.source.stb.eq(1),
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self.source.data.eq(Replicate(KCode["pak_end"], 4)),
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self.source.k.eq(Replicate(1, 4)),
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# Simulate RX don't have eop tagged
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# self.source.eop.eq(1),
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If(self.source.ack, NextState("IDLE")),
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)
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# With KCode & 0x01*4
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class StreamData_Generator(Module):
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def __init__(self):
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# should be big enough for all test
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self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
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self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
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self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
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# # #
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pipeline = [buffer, crc_inserter, wrapper]
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# For verifying crc in stream data packet
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class Double_Stream_Buffer(Module):
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# default size is 2 kBtyes - Section 9.5.2 (CXP-001-2021)
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def __init__(self, size=16000):
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# detect and tag end of packet for crc
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# self.submodules.eop_marker = eop_marker = EOP_Marker()
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# self.sink = eop_marker.sink
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self.sink = stream.Endpoint(word_layout_dchar)
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self.submodules.crc = crc = CXPCRC32(word_dw)
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self.comb += crc.data.eq(self.sink.data)
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self.submodules.fsm = fsm = FSM(reset_state="RESET")
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write_mask = Signal()
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self.submodules.line_buffer0 = line_buffer0 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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self.submodules.line_buffer1 = line_buffer1 = ResetInserter()(stream.SyncFIFO(word_layout_dchar, 2**bits_for(size//word_dw)))
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fsm.act("RESET",
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Case(write_mask,
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{
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0: line_buffer0.reset.eq(1),
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1: line_buffer1.reset.eq(1),
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}
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),
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crc.reset.eq(1),
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NextState("CHECKING"),
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)
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fsm.act("CHECKING",
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self.sink.ack.eq(1),
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If(self.sink.stb,
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crc.ce.eq(1),
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If(self.sink.eop,
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# discard the crc at the end
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NextState("SWITCH_BUFFER")
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).Else(
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If(write_mask == 0,
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self.sink.connect(line_buffer0.sink),
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).Else(
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self.sink.connect(line_buffer1.sink),
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),
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)
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)
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)
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# only valid data will be passed to downstream
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fsm.act("SWITCH_BUFFER",
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If(~crc.error,
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NextValue(write_mask, ~write_mask),
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),
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NextState("RESET"),
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)
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self.submodules.mux = mux = stream.Multiplexer(word_layout_dchar, 2)
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self.comb += [
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line_buffer0.source.connect(mux.sink0),
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line_buffer1.source.connect(mux.sink1),
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mux.sel.eq(~write_mask),
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]
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self.source = mux.source
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# DEBUG:
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self.write = Signal()
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|
self.error = Signal()
|
||
|
|
self.comb += [
|
||
|
|
self.write.eq(write_mask),
|
||
|
|
self.error.eq(crc.error),
|
||
|
|
]
|
||
|
|
|
||
|
|
# # to add eop in the same cycle
|
||
|
|
# # the tricks relies on the fact source lags sink one cycle
|
||
|
|
# # but fsm .connect by default use combinational logic which the same cycle rising/falling edge check immpossible
|
||
|
|
# fsm.act("CHECKING",
|
||
|
|
# NextValue(self.source.payload.raw_bits(), 0),
|
||
|
|
# NextValue(self.source.stb, 0),
|
||
|
|
# If(self.sink.stb,
|
||
|
|
# crc.ce.eq(1),
|
||
|
|
# If(self.sink.eop,
|
||
|
|
# NextState("RESET")
|
||
|
|
# ).Else(
|
||
|
|
# NextValue(self.source.payload.raw_bits(), self.sink.payload.raw_bits()),
|
||
|
|
# NextValue(self.source.stb, 1),
|
||
|
|
# )
|
||
|
|
# )
|
||
|
|
# )
|
||
|
|
|
||
|
|
# last_eop = Signal()
|
||
|
|
# self.comb += self.source.eop.eq(~last_eop & self.sink.eop)
|