forked from M-Labs/artiq-zynq
13 lines
506 B
Python
13 lines
506 B
Python
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# Clocking/Reset
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# Create rio and rio_phy domains based on sys
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# with reset controlled by CSR.
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#
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# The `rio` CD contains logic that is reset with `core.reset()`.
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# That's state that could unduly affect subsequent experiments,
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# i.e. input overflows caused by input gates left open, FIFO events far
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# in the future blocking the experiment, pending RTIO or
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# wishbone bus transactions, etc.
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# The `rio_phy` CD contains state that is maintained across
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# `core.reset()`, i.e. TTL output state, OE, DDS state.
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