forked from M-Labs/artiq-zynq
73 lines
2.2 KiB
Python
73 lines
2.2 KiB
Python
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from migen import *
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from misoc.interconnect.csr import *
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from misoc.interconnect import stream
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from sim_generator import CXPCRC32Inserter
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from src.gateware.cxp_frame_pipeline import *
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from src.gateware.cxp_pipeline import *
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class EOP_Pipeline(Module):
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def __init__(self):
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dchar_decoder = Duplicated_Char_Decoder()
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eop_inserter = EOP_Inserter()
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buffer = stream.SyncFIFO(word_layout_dchar, 32)
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pipeline = [dchar_decoder, eop_inserter, buffer]
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self.submodules += pipeline
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for s, d in zip(pipeline, pipeline[1:]):
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self.comb += s.source.connect(d.sink)
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self.sink = pipeline[0].sink
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self.source = pipeline[-1].source
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# for sim, no backpressure
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self.comb += self.source.ack.eq(1)
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dut = EOP_Pipeline()
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def packet_sim(packets=[]):
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print("=================TEST========================")
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sink = dut.sink
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cyc = len(packets)
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pak = packets
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for c in range(cyc):
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yield sink.data.eq(pak[c]["data"])
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yield sink.k.eq(pak[c]["k"])
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yield sink.stb.eq(1)
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yield
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# extra clk cycles
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for _ in range(cyc, cyc + 10):
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yield sink.data.eq(0)
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yield sink.k.eq(0)
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yield sink.stb.eq(0)
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yield sink.eop.eq(0)
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yield
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assert True
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def testbench():
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paks = [
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{"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
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{"data": C(0x1111, word_dw), "k": Replicate(1, 4)},
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{"data": C(0x2222, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x3333, word_dw), "k": Replicate(0, 4)},
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{"data": C(0x4444, word_dw), "k": Replicate(0, 4)},
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{"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
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{"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
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{"data": C(0xAAAA, word_dw), "k": Replicate(1, 4)},
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{"data": C(0xBBBB, word_dw), "k": Replicate(0, 4)},
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{"data": C(0xCCCC, word_dw), "k": Replicate(0, 4)},
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{"data": C(0xDDDD, word_dw), "k": Replicate(0, 4)},
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{"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
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]
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yield from packet_sim(paks)
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run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")
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