temp note: update

sim: add double buffer
sim: add eop marker for crc checker in double buffer
sim: add KCode, pak type & CRC generator
sim: add Stream crossbar
sim: add stream pipeline with parser & buffer
sim: add frame generator & image viewer
sim: add arbiter
sim: add broadcaster, double buffer & eop tester

sim: add roi pipeline

sim: update roi

.pre-commit-config.yaml

@@ -0,0 +1,8 @@
+repos: 
+  - repo: local
+    hooks:
+      - id: cargo_format
+        name: cargo_format
+        entry: cargofmt.sh
+        language: script
+        pass_filenames: false

build_CI.sh

@@ -0,0 +1,38 @@
+#!/usr/bin/env bash
+
+set -e
+
+if [ -z "$OPENOCD_ZYNQ" ]; then
+    echo "OPENOCD_ZYNQ environment variable must be set"
+    exit 1
+fi
+if [ -z "$SZL" ]; then
+    echo "SZL environment variable must be set"
+    exit 1
+fi
+
+
+# variant="firmware"
+# variant="gateware"
+# variant="jtag"
+variant="sd"
+
+nix build .#kasli_soc-demo-$variant -L
+nix build .#kasli_soc-master-$variant -L
+nix build .#kasli_soc-satellite-$variant -L
+
+# nix build .#zc706-acpki_nist_clock-$variant -L
+# nix build .#zc706-acpki_nist_clock_master-$variant -L
+# nix build .#zc706-acpki_nist_clock_satellite-$variant -L
+
+# nix build .#zc706-acpki_nist_qc2-$variant -L
+# nix build .#zc706-acpki_nist_qc2_master-$variant -L
+# nix build .#zc706-acpki_nist_qc2_satellite-$variant -L
+
+# nix build .#zc706-nist_clock-$variant -L
+# nix build .#zc706-nist_clock_master-$variant -L
+# nix build .#zc706-nist_clock_satellite-$variant -L
+
+# nix build .#zc706-nist_qc2-$variant -L
+# nix build .#zc706-nist_qc2_master-$variant -L
+# nix build .#zc706-nist_qc2_satellite-$variant -L

cargofmt.sh

@@ -0,0 +1,5 @@
+#!/usr/bin/env bash
+
+nix-shell -p gnumake --command 'make manifests -B'
+cd src
+cargo fmt -- --check

coaxpress.drawio

@@ -0,0 +1,338 @@
+<mxfile host="65bd71144e">
+    <diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
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+                </mxCell>
+                <mxCell id="40" value="White: clocked by sys (125MHz)" style="rounded=0;whiteSpace=wrap;html=1;labelBackgroundColor=none;strokeColor=default;fontColor=#000000;fillColor=default;align=left;" parent="1" vertex="1">
+                    <mxGeometry x="120" y="800" width="360" height="40" as="geometry"/>
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+                <mxCell id="43" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;b&gt;&lt;u&gt;CXP Bootstrap FW&lt;/u&gt;&lt;/b&gt;&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle GTX speed&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- test connection&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- hand over to RTIO after init&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;span style=&quot;white-space: pre;&quot;&gt;&#9;&lt;/span&gt;- cannot access CTRL PAK&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- with camera specific .rs file&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- compare heatbeat to check connection status&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle event ack??&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- don't use tag?&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;align=center;fillColor=#fff2cc;strokeColor=#d6b656;" parent="1" vertex="1">
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+                <mxCell id="53" value="&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&lt;u&gt;&lt;b&gt;CXP Camera specific prog&lt;/b&gt;&lt;/u&gt;&lt;br&gt;GenICam interface @&amp;nbsp;&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;RTIO coredevice&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle frame programming&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- handle event as well??&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- two interface&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- IO CTRL packet via API!&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- on master ch only&lt;/span&gt;&lt;/div&gt;&lt;div style=&quot;text-align: justify;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;&amp;nbsp; &amp;nbsp;- O Frame data&lt;/span&gt;&lt;/div&gt;" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" parent="1" vertex="1">
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+                <mxCell id="185" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- 32bit pixel data&lt;/span&gt;&lt;/div&gt;- frame valid (new frame)&lt;br&gt;- line break" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
+                    <mxGeometry x="1520" y="-430" width="160" height="60" as="geometry"/>
+                </mxCell>
+                <mxCell id="186" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
+                    <mxGeometry x="920" y="-360.42" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="187" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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+                        <mxPoint x="1080" y="-320.87000000000006" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="188" value="Double&lt;br&gt;Buffered&lt;br&gt;Memory" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
+                    <mxGeometry x="1080" y="-360.42" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="194" value="Pixel Decoder" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#fad9d5;strokeColor=#ae4132;" parent="1" vertex="1">
+                    <mxGeometry x="1400" y="-360" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="195" value="&lt;div style=&quot;&quot;&gt;&lt;span style=&quot;background-color: initial;&quot;&gt;- extract line break &amp;amp; new frame&lt;/span&gt;&lt;/div&gt;" style="text;html=1;align=left;verticalAlign=middle;resizable=0;points=[];autosize=1;strokeColor=none;fillColor=none;" parent="1" vertex="1">
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+                <mxCell id="203" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="205" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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+                        <mxPoint x="920" y="-320.0400000000001" as="targetPoint"/>
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+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="206" value="CRC Checker" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;" parent="1" vertex="1">
+                    <mxGeometry x="920" y="-480" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="207" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;dashed=1;" parent="1" edge="1">
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+                        <mxPoint x="1080" y="-440.45000000000016" as="targetPoint"/>
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+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="208" value="Double&lt;br&gt;Buffered&lt;br&gt;Memory" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;dashed=1;" parent="1" vertex="1">
+                    <mxGeometry x="1080" y="-480" width="80" height="80" as="geometry"/>
+                </mxCell>
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+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="210" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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+                        <mxPoint x="680" y="-280.00000000000017" as="sourcePoint"/>
+                        <mxPoint x="760" y="-279.62000000000006" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="211" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
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+                        <mxPoint x="680" y="-360.00000000000017" as="sourcePoint"/>
+                        <mxPoint x="760" y="-359.62000000000006" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="212" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
+                    <mxGeometry width="100" relative="1" as="geometry">
+                        <mxPoint x="680" y="-200.49000000000018" as="sourcePoint"/>
+                        <mxPoint x="760" y="-200.11000000000007" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="213" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;dashed=1;" parent="1" edge="1">
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+                        <mxPoint x="840" y="-440.42000000000036" as="sourcePoint"/>
+                        <mxPoint x="920" y="-440.04000000000025" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="214" value="Stream&lt;br&gt;Parser" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" parent="1" vertex="1">
+                    <mxGeometry x="1240" y="-360.00000000000006" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="215" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" parent="1" edge="1">
+                    <mxGeometry width="100" relative="1" as="geometry">
+                        <mxPoint x="1320" y="-320.41999999999996" as="sourcePoint"/>
+                        <mxPoint x="1400" y="-320.03999999999985" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="216" value="Streams&lt;br&gt;Crossbar" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" vertex="1" parent="1">
+                    <mxGeometry x="800" y="-40" width="80" height="200" as="geometry"/>
+                </mxCell>
+                <mxCell id="217" value="Stream pipeline #1" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#f8cecc;strokeColor=#b85450;" vertex="1" parent="1">
+                    <mxGeometry x="960" y="80" width="80" height="80" as="geometry"/>
+                </mxCell>
+                <mxCell id="218" value="" style="edgeStyle=none;orthogonalLoop=1;jettySize=auto;html=1;" edge="1" parent="1">
+                    <mxGeometry width="100" relative="1" as="geometry">
+                        <mxPoint x="880" y="119.57999999999993" as="sourcePoint"/>
+                        <mxPoint x="960" y="119.96000000000004" as="targetPoint"/>
+                        <Array as="points"/>
+                    </mxGeometry>
+                </mxCell>
+            </root>
+        </mxGraphModel>
+    </diagram>
+</mxfile>

cxp_kernel.py

@@ -0,0 +1,310 @@
+"""
+Non-realtime drivers for CXP.
+"""
+
+# TODO: add api calls for CTRL packet similar i2c
+# TODO: add timing critical trigger ack
+
+
+from artiq.language.core import syscall, kernel
+from artiq.language.types import TBool, TInt32, TNone
+from artiq.coredevice.rtio import rtio_output
+from artiq.experiment import *
+import numpy as np
+import math
+
+
+# TODO: change this to read bytes and accept TBytearray 
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_read_words(addr: TInt32, val: TList(TInt32), with_tag: TBool) -> TInt32:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_readu32(addr: TInt32, with_tag: TBool) -> TInt32:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_readu64(addr: TInt32, with_tag: TBool) -> TInt64:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_writeu32(addr: TInt32, val: TInt32, with_tag: TBool) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_writeu64(addr: TInt32, val: TInt64, with_tag: TBool) -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_setup() -> TBool:
+    raise NotImplementedError("syscall not simulated")
+
+
+@syscall(flags={"nounwind", "nowrite"})
+def cxp_debug_frame_print() -> TNone:
+    raise NotImplementedError("syscall not simulated")
+
+
+# Bootstrap register
+_XML_MANIFEST_SIZE = 0x0008
+_XML_MANIFEST_SEL = 0x000C
+_XML_VER = 0x0010
+_XML_SCHEMA_VER = 0x0014
+_XML_URL_ADDR = 0x0018
+_WIDTH_ADDR = 0x3000
+_HEIGHT_ADDR = 0x3004
+_ACQUISITION_MODE_ADDR = 0x3008
+_ACQUISITION_START_ADDR = 0x300C
+_ACQUISITION_STOP_ADDR = 0x3010
+_PIXEL_FORMAT_ADDR = 0x3014
+_DEVICE_TAP_GEOG_ADDR = 0x3018
+_IMG_1_STREAMID_ADDR = 0x301C
+
+_MAX_BYTE_SIZE = 100  # in bytes
+_MAX_WORD_SIZE = _MAX_BYTE_SIZE // 4  # in bytes
+
+
+class CoaXPress:
+    def __init__(self, channel, core_device="core", xml_url_len=_MAX_WORD_SIZE):
+        # __device_mgr is private
+        # self.core = dmgr.get(core_device)
+
+        # you can get the channel via `print(len(rtio_channels))` before calling
+        # `rtio_channels.append(rtio.Channel.from_phy(cxp_interface))`
+        self.channel = channel
+        # the first 8 bits is reserved for the rtlink.OInterface.addr not for channel no.
+        self.target_o = channel << 8
+
+        self.with_tag = False
+
+        self.xml_addr = 0
+        self.width_addr = 0
+        self.height_addr = 0
+        self.acq_mode_addr = 0
+        self.acq_start_addr = 0
+        self.acq_stop_addr = 0
+        self.pixel_fmt_addr = 0
+        self.device_tap_geog_addr = 0
+        self.img_1_streamid_addr = 0
+
+        self.xml_url = [0] * xml_url_len
+
+    @staticmethod
+    def get_rtio_channels(channel, **kwargs):
+        return [(channel, None)]
+
+    @kernel
+    def trigger(self, linktrig, trigdelay):
+        rtio_output(self.target_o, linktrig | trigdelay << 1)
+
+    @kernel
+    def init(self):
+        self.with_tag = cxp_setup()
+
+        self.xml_addr = self.read_u32(_XML_URL_ADDR)
+        # self.width_addr = self.read_u32(_WIDTH_ADDR)
+        # self.height_addr = self.read_u32(_HEIGHT_ADDR)
+        self.acq_mode_addr = self.read_u32(_ACQUISITION_MODE_ADDR)
+        self.acq_start_addr = self.read_u32(_ACQUISITION_START_ADDR)
+        self.acq_stop_addr = self.read_u32(_ACQUISITION_STOP_ADDR)
+        self.pixel_fmt_addr = self.read_u32(_PIXEL_FORMAT_ADDR)
+        # self.device_tap_geog_addr = self.read_u32(_DEVICE_TAP_GEOG_ADDR)
+        self.img_1_streamid_addr = self.read_u32(_IMG_1_STREAMID_ADDR)
+
+        self.read_words(self.xml_addr, self.xml_url)
+
+    @kernel
+    def read_u32(self, addr: TInt32) -> TInt32:
+        return cxp_readu32(addr, self.with_tag)
+
+    @kernel
+    def read_u64(self, addr: TInt32) -> TInt64:
+        return cxp_readu64(addr, self.with_tag)
+
+    @kernel
+    def read_words(self, addr: TInt32, val: TList(TInt32)):
+        cxp_read_words(addr, val, self.with_tag)
+
+    @kernel
+    def write_u32(self, addr: TInt32, val: TInt32):
+        cxp_writeu32(addr, val, self.with_tag)
+
+    @kernel
+    def write_u64(self, addr: TInt32, val: TInt64):
+        cxp_writeu64(addr, val, self.with_tag)
+
+    @kernel
+    def write_wide(self, addr: TInt32, vals: TList(TInt32)):
+        for i in range(len(vals)):
+            cxp_writeu32(addr + i * 4, vals[i], self.with_tag)
+
+    @kernel
+    def read_width(self) -> TInt32:
+        return self.read_u32(self.width_addr)
+
+    @kernel
+    def read_height(self) -> TInt32:
+        return self.read_u32(self.height_addr)
+
+    @kernel
+    def read_acq_mode(self) -> TInt64:
+        return self.read_u64(self.acq_mode_addr)
+
+    @kernel
+    def write_acq_mode(self, val: TInt64):
+        self.write_u64(self.acq_mode_addr, val)
+
+    @kernel
+    def start(self):
+        self.write_u32(self.acq_start_addr, 0x00000001)
+
+    @kernel
+    def stop(self):
+        self.write_u32(self.acq_stop_addr, 0x00000001)
+
+    @kernel
+    def get_frameid(self) -> TInt32:
+        return self.read_u32(self.img_1_streamid_addr)
+
+    @kernel
+    def get_pixel_format(self) -> TInt32:
+        return self.read_u32(self.pixel_fmt_addr)
+
+    @host_only
+    def print_xml_url(self):
+        url = ""
+        for x in self.xml_url:
+            url += x.to_bytes(4, byteorder="big").decode("ascii")
+        print(f"url = {url}")
+        if "Local:" in url:
+            file_name, start_addr, size = url.split(";", 2)
+            print(
+                f"file name: {file_name.replace("Local:", "")}, start addr: 0x{start_addr}, size; 0x{size.split("?", 1)[0]} bytes"
+            )
+
+    @kernel
+    def get_xml_data(self, xml_start_addr, xml_data):
+        i = -1
+        addr_offset = 0
+        for i in range(len(xml_data) // _MAX_WORD_SIZE):
+            buf = [0] * _MAX_WORD_SIZE
+            self.read_words(xml_start_addr + addr_offset, buf)
+            for j in range(len(buf)):
+                xml_data[j+i*_MAX_WORD_SIZE] = buf[j]
+
+            addr_offset += _MAX_WORD_SIZE * 4
+
+        buf = [0]*(len(xml_data) % _MAX_WORD_SIZE)
+        self.read_words(xml_start_addr + addr_offset, buf)
+        for j in range(len(buf)):
+            xml_data[j+(i+1)*_MAX_WORD_SIZE] = buf[j]
+
+    @host_only
+    def write_xml_data(self, xml_data, file_path):
+        byte_arr = bytearray()
+        for d in xml_data:
+            byte_arr += d.to_bytes(4, "big", signed=True)
+        with open(file_path, "wb") as binary_file:
+            binary_file.write(byte_arr)
+
+
+# From the camera XML files
+_USER_SET_SELECTOR = 0x10000050
+_REAL_ACQ_MODE = 0x10000bb4
+_REAL_ACQ_START = 0x10000498
+_REAL_ACQ_STOP = 0x100004a4
+_REAL_ACQ_ABORT = 0x100004b0 #stop all acq immediately
+_BSL_SENSOR_STAND_BY = 0x100004c8 # put sensor in standby mode, certain parameter can only be change during standby
+_BSL_POWER_MODE = 0x100000b4
+# strange d_470 -> d_469 (= 3) perhaps a obscure security trick? So I guess looking @ Index"3" is fine?
+_TRIG_MODE_INDEX_3 = 0x10001424 # d_87
+_TRIG_SRC_INDEX_3 = 0x100081ac # d_479
+_TRIG_ACT_INDEX_3 = 0x1000293c # d_502
+_TRIG_SOFTWARE_INDEX_3 = 0x10000c34 # d_525
+
+CXP_TRIG = True
+
+class IdleKernel(EnvExperiment):
+    def build(self):
+        self.setattr_device("core")
+        self.setattr_device("led0")
+
+        # declare the class before using it in kernel
+        self.cxp = CoaXPress(0x0)
+        # self.vals = [0]*0x11ab3
+
+        xml_word_size = math.ceil(0x11ab3/4)
+        self.vals = [0] * xml_word_size
+    @kernel
+    def camera_setup(self):
+        self.cxp.init()
+
+        # DEBUG: get xml data
+        # self.cxp.get_xml_data(0xc0000000, self.vals)
+
+
+        # DEBUG: Try to setup trigger
+        # All address below is from the XML, what's the point of bootstrap anyway?
+        # NOTE: setting is persistent over ConnectionReset but NOT power cycle
+        # self.cxp.write_u32(_REAL_ACQ_MODE, 1) # single frame mode
+        # self.cxp.write_u32(_REAL_ACQ_START, 1) # single acq start
+        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
+        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
+
+        # boA2448-250cm is area scan camera:
+        # see https://docs.baslerweb.com/triggered-image-acquisition#hardware-and-software-triggering to setup triggering properly
+
+        # TRIGGER: setup
+        # self.cxp.write_u32(_TRIG_SELECTOR, 3) # FrameStart by default, boA xml b_469 don't have an address for some reason
+        self.cxp.write_u32(_TRIG_MODE_INDEX_3, 1) # ON
+        if CXP_TRIG:
+            self.cxp.write_u32(_TRIG_SRC_INDEX_3, 7) # CXPTrigger0
+        else:
+            self.cxp.write_u32(_TRIG_SRC_INDEX_3, 0) # use software trigger 
+        self.cxp.write_u32(_TRIG_ACT_INDEX_3, 2) # trig on anyedge
+        
+        cxp_debug_frame_print()
+
+        # TAKING PICTURE
+        self.cxp.write_u32(_REAL_ACQ_MODE, 1) # single frame mode
+        self.cxp.write_u32(_REAL_ACQ_START, 1) # single acq start
+
+        # STOP acq
+        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
+        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
+        
+        # self.cxp.write_u32(_BSL_SENSOR_STAND_BY, 1)
+        return self.cxp.read_u32(_BSL_POWER_MODE)
+
+    @kernel
+    def kernel(self):
+        # reset mu for rtio
+        self.core.reset()
+        self.core.break_realtime()
+
+        if CXP_TRIG:
+            self.cxp.trigger(0 ,0x00)
+        else:
+            self.cxp.write_u32(_TRIG_SOFTWARE_INDEX_3, 0) # software trigger via register write
+        
+        # self.cxp.write_u32(_REAL_ACQ_STOP, 1) # single acq end
+        # self.cxp.write_u32(_REAL_ACQ_ABORT, 1) # single acq ABORT
+        # self.cxp.write_u32(_BSL_SENSOR_STAND_BY, 1)
+        for _ in range(4):
+            cxp_debug_frame_print()
+
+        return 0
+
+    def print_hex(self, arr: TList(TInt32)):
+        print("[{}]".format(", ".join(hex(np.uint32(x)) for x in arr)))
+
+    def run(self):
+        print(f"power mode = {self.camera_setup()}")
+        self.kernel()
+        # self.cxp.print_xml_url()
+        # self.cxp.write_xml_data(self.vals, "genicam_16e13898.zip")

cxp_note.md

@@ -0,0 +1,60 @@
+# CXP
+
+## Finished
+- Upconn - Low speed serial 
+  [x] Low speed serial PHY
+    [x] 20.833Mbps & 41.666Mbps change
+    [x] 8b10b encoder
+  [x] TX Pipeline with priority transmission
+    [x] Trigger
+    [x] Trigger ack
+    [x] Test & Ctrl packet with DMA
+  [x] CTRL Packet serialize firmware
+    [x] follow DRTIO DMA
+    [x] check crc
+- Downconn - GTX
+  [x] GTX serial PHY
+    [x] QPLL & GTX DRP to config linerate
+    [x] Comma checker & restart rx
+  [x] RX Pipeline with priority decoder
+    [x] Trigger ack 
+    [x] CTRL packet DMA with extra buffer
+    [x] Connection test sequence checker
+  [x] CTRL Packet deserialize firmware
+    [x] follow DRTIO DMA
+    [x] check crc
+  [x] GTX Multilane setup
+- Camera boostrap
+  [x] get the CXP version
+  [x] test connection
+  [x] discovery other extension (links)
+  [x] set bitrate
+- Camera frame pipeline
+  [x] CXP frame packet routing (maybe no need to routing non zero streaming id (we have ROI buildin anyways)?)
+  [x] CXP CRC32 detection
+
+
+## TODO
+[] remove ALL debug tools
+  [] flake.nix mod
+  [] local_run.sh mod
+### Gateware
+[] Test out CXP trigger
+[] Region of interest engine
+[] rtio to getting the frame
+  - O: trigger
+  - I: frame
+
+### Firmware
+[] Camera linkdown detection
+[] Camera auto linkup/linkdown using threads
+[] API programming
+[] add tag handling for api calls
+  - support line reset in kernel using syscall
+[] add heartbeat checking
+
+### Coredevice Driver
+[] support simple camera programming interface (Not real time)
+  - basic i2c-like interface with read/write u32
+
+

device_db.py

@@ -0,0 +1,30 @@
+device_db = {
+    "core": {
+        "type": "local",
+        "module": "artiq.coredevice.core",
+        "class": "Core",
+        "arguments": {
+            "host": "192.168.1.14",
+            "ref_period": 1e-9,
+            "ref_multiplier": 8,
+            "target": "cortexa9"
+        }
+    },
+    "core_cache": {
+        "type": "local",
+        "module": "artiq.coredevice.cache",
+        "class": "CoreCache"
+    },
+    "core_dma": {
+        "type": "local",
+        "module": "artiq.coredevice.dma",
+        "class": "CoreDMA"
+    },
+
+    "led0": {
+        "type": "local",
+        "module": "artiq.coredevice.ttl",
+        "class": "TTLOut",
+        "arguments": {"channel": 0x000001},
+    },
+}

flake.lock

@@ -11,11 +11,11 @@
         "src-pythonparser": "src-pythonparser"
       },
       "locked": {
-        "lastModified": 1732066716,
-        "narHash": "sha256-krjvt9+RccnAxSEZcFhRpjA2S3CoqE4MSa1JUg421b4=",
+        "lastModified": 1725373154,
+        "narHash": "sha256-fq9EW9fDWrV0v1vNj7ZqDNpNYx8+OxoFdPwpvkPf67g=",
         "ref": "refs/heads/master",
-        "rev": "270a417a28b516d36983779a1adb6d33a3c55a4a",
-        "revCount": 9102,
+        "rev": "0c1ffa9f4f6a3e7864459923ec4b9cc45f16327a",
+        "revCount": 9005,
         "type": "git",
         "url": "https://github.com/m-labs/artiq.git"
       },
@@ -70,11 +70,11 @@
     },
     "nixpkgs": {
       "locked": {
-        "lastModified": 1731319897,
-        "narHash": "sha256-PbABj4tnbWFMfBp6OcUK5iGy1QY+/Z96ZcLpooIbuEI=",
+        "lastModified": 1724224976,
+        "narHash": "sha256-Z/ELQhrSd7bMzTO8r7NZgi9g5emh+aRKoCdaAv5fiO0=",
         "owner": "NixOS",
         "repo": "nixpkgs",
-        "rev": "dc460ec76cbff0e66e269457d7b728432263166c",
+        "rev": "c374d94f1536013ca8e92341b540eba4c22f9c62",
         "type": "github"
       },
       "original": {
@@ -84,9 +84,26 @@
         "type": "github"
       }
     },
+    "nixpkgs_old": {
+      "locked": {
+        "lastModified": 1720535198,
+        "narHash": "sha256-zwVvxrdIzralnSbcpghA92tWu2DV2lwv89xZc8MTrbg=",
+        "owner": "nixos",
+        "repo": "nixpkgs",
+        "rev": "205fd4226592cc83fd4c0885a3e4c9c400efabb5",
+        "type": "github"
+      },
+      "original": {
+        "owner": "nixos",
+        "ref": "nixos-23.11",
+        "repo": "nixpkgs",
+        "type": "github"
+      }
+    },
     "root": {
       "inputs": {
         "artiq": "artiq",
+        "nixpkgs_old": "nixpkgs_old",
         "zynq-rs": "zynq-rs"
       }
     },
@@ -158,11 +175,11 @@
     "src-migen": {
       "flake": false,
       "locked": {
-        "lastModified": 1727677091,
-        "narHash": "sha256-Zg3SQnTwMM/VkOGKogbPyuCC2NhLy8HB2SPEUWWNgCU=",
+        "lastModified": 1724304798,
+        "narHash": "sha256-tQ02N0eXY5W/Z7CrOy3Cu4WjDZDQWb8hYlzsFzr3Mus=",
         "owner": "m-labs",
         "repo": "migen",
-        "rev": "c19ae9f8ae162ffe2d310a92bfce53ac2a821bc8",
+        "rev": "832a7240ba32af9cbd4fdd519ddcb4f912534726",
         "type": "github"
       },
       "original": {
@@ -245,4 +262,4 @@
   },
   "root": "root",
   "version": 7
-}
+}

flake.nix

@@ -5,12 +5,16 @@
   inputs.zynq-rs.url = git+https://git.m-labs.hk/m-labs/zynq-rs;
   inputs.zynq-rs.inputs.nixpkgs.follows = "artiq/nixpkgs";
 
-  outputs = { self, zynq-rs, artiq }:
+  inputs.nixpkgs_old.url = "github:nixos/nixpkgs?ref=nixos-23.11";
+
+  outputs = { self, zynq-rs, artiq, nixpkgs_old }:
   let
+    pkgs_old = import nixpkgs_old { system = "x86_64-linux";};
     pkgs = import artiq.inputs.nixpkgs { system = "x86_64-linux"; overlays = [ (import zynq-rs.inputs.rust-overlay) ]; };
     zynqpkgs = zynq-rs.packages.x86_64-linux;
     artiqpkgs = artiq.packages.x86_64-linux;
-    llvmPackages_11 = zynq-rs.llvmPackages_11;
+    # llvmPackages_11 = zynq-rs.llvmPackages_11;
+    llvmPackages_11 = pkgs_old.llvmPackages_11;
 
     rust = zynq-rs.rust;
     rustPlatform = zynq-rs.rustPlatform;
@@ -341,6 +345,7 @@
       {
         inherit fastnumbers artiq-netboot ramda migen-axi binutils-arm;
       } //
+      (board-package-set { target = "zc706"; variant = "cxp_demo"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master"; }) //
       (board-package-set { target = "zc706"; variant = "nist_clock_master_100mhz"; }) //
@@ -380,7 +385,7 @@
         zynqpkgs.mkbootimage
         openocd  
         openssh rsync
-        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ])))
+        (python3.withPackages(ps: (with artiqpkgs; [ migen migen-axi misoc artiq artiq-netboot ps.jsonschema ps.pyftdi ps.pillow ])))
         artiqpkgs.artiq
         artiqpkgs.vivado
         binutils-arm

local_run.sh

@@ -13,7 +13,7 @@ fi
 
 impure=0
 load_bitstream=1
-board_type="kasli_soc"
+board_type="zc706"
 fw_type="runtime"
 
 while getopts "ilb:t:f:" opt; do
@@ -36,7 +36,7 @@ done
 if [ -z "$board_host" ]; then
     case $board_type in
     kasli_soc) board_host="192.168.1.56";;
-    zc706) board_host="192.168.1.52";;
+    zc706) board_host="192.168.1.14";;
     *) echo "Unknown board type"; exit 1;;
     esac
 fi
@@ -58,4 +58,4 @@ else
         load_bitstream_cmd="-g $result_dir/top.bit"
     fi
     artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
-fi
+fi

notes.drawio

@@ -0,0 +1,82 @@
+<mxfile host="65bd71144e">
+    <diagram id="en7HUHNV3kVsTTCxeEt8" name="Page-1">
+        <mxGraphModel dx="924" dy="545" grid="1" gridSize="10" guides="1" tooltips="1" connect="1" arrows="1" fold="1" page="0" pageScale="1" pageWidth="850" pageHeight="1100" background="none" math="0" shadow="0">
+            <root>
+                <mxCell id="0"/>
+                <mxCell id="1" parent="0"/>
+                <mxCell id="50" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="280" y="200" as="sourcePoint"/>
+                        <mxPoint x="440" y="200" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="52" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="50">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="-63" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="53" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="280" y="239.81" as="sourcePoint"/>
+                        <mxPoint x="440" y="239.81" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="54" value="stb (valid/readable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="53">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="-63" y="-1" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="55" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="440" y="279.80999999999995" as="sourcePoint"/>
+                        <mxPoint x="280" y="279.80999999999995" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="56" value="ack (ready)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="55">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="-197" y="1" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="48" value="Source" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#d5e8d4;strokeColor=#82b366;" vertex="1" parent="1">
+                    <mxGeometry x="320" y="160" width="80" height="160" as="geometry"/>
+                </mxCell>
+                <mxCell id="57" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="520" y="200" as="sourcePoint"/>
+                        <mxPoint x="680" y="200" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="58" value="Payload (layout)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="57">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="197" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="59" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="520" y="239.80999999999995" as="sourcePoint"/>
+                        <mxPoint x="680" y="239.80999999999995" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="60" value="stb (valid)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="59">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="197" y="-1" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="61" value="" style="shape=flexArrow;endArrow=classic;html=1;fillColor=#647687;strokeColor=#314354;" edge="1" parent="1">
+                    <mxGeometry width="50" height="50" relative="1" as="geometry">
+                        <mxPoint x="680" y="279.99999999999994" as="sourcePoint"/>
+                        <mxPoint x="520" y="279.99999999999994" as="targetPoint"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="62" value="ack (ready/writeable)" style="edgeLabel;html=1;align=center;verticalAlign=middle;resizable=0;points=[];" vertex="1" connectable="0" parent="61">
+                    <mxGeometry x="-0.8404" y="-1" relative="1" as="geometry">
+                        <mxPoint x="73" y="1" as="offset"/>
+                    </mxGeometry>
+                </mxCell>
+                <mxCell id="49" value="Sink" style="rounded=0;whiteSpace=wrap;html=1;fillColor=#ffe6cc;strokeColor=#d79b00;" vertex="1" parent="1">
+                    <mxGeometry x="560" y="160" width="80" height="160" as="geometry"/>
+                </mxCell>
+            </root>
+        </mxGraphModel>
+    </diagram>
+</mxfile>

reset.py

@@ -0,0 +1,17 @@
+from time import sleep
+from pyftdi.ftdi import Ftdi
+
+POR = 1 << 7
+
+def main():
+    dev = Ftdi()
+    dev.open_bitbang_from_url("ftdi://ftdi:4232h/0")
+    dev.set_bitmode(POR, Ftdi.BitMode.BITBANG)
+    dev.write_data(bytes([0]))
+    sleep(0.1)
+    dev.write_data(bytes([POR]))
+    sleep(0.1)
+    dev.close()
+
+if __name__ == "__main__":
+    main()

sat_run.sh

@@ -0,0 +1,63 @@
+#!/usr/bin/env bash
+
+python reset.py
+
+set -e
+
+if [ -z "$OPENOCD_ZYNQ" ]; then
+    echo "OPENOCD_ZYNQ environment variable must be set"
+    exit 1
+fi
+if [ -z "$SZL" ]; then
+    echo "SZL environment variable must be set"
+    exit 1
+fi
+
+impure=0
+load_bitstream=1
+board_type="kasli_soc"
+fw_type="satman"
+
+while getopts "ilb:t:f:" opt; do
+    case "$opt" in
+    \?) exit 1
+        ;;
+    i)  impure=1
+        ;;
+    l)  load_bitstream=0
+        ;;
+    b)  board_host=$OPTARG
+        ;;
+    t)  board_type=$OPTARG
+        ;;
+    f)  fw_type=$OPTARG
+        ;;
+    esac
+done
+
+if [ -z "$board_host" ]; then
+    case $board_type in
+    kasli_soc) board_host="192.168.1.56";;
+    zc706) board_host="192.168.1.52";;
+    *) echo "Unknown board type"; exit 1;;
+    esac
+fi
+
+load_bitstream_cmd=""
+
+build_dir=`pwd`/build
+result_dir=`pwd`/result
+cd $OPENOCD_ZYNQ
+openocd -f $board_type.cfg -c "load_image $SZL/szl-$board_type.elf; resume 0; exit"
+sleep 5
+if [ $impure -eq 1 ]; then
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g $build_dir/gateware/top.bit"
+    fi
+    artiq_netboot $load_bitstream_cmd -f $build_dir/$fw_type.bin -b $board_host
+else
+    if [ $load_bitstream -eq 1 ]; then
+        load_bitstream_cmd="-g $result_dir/top.bit"
+    fi
+    artiq_netboot $load_bitstream_cmd -f $result_dir/$fw_type.bin -b $board_host
+fi

sim.py

@@ -0,0 +1,55 @@
+from migen import *
+from misoc.interconnect.csr import *
+
+from functools import reduce
+from itertools import combinations
+from operator import or_, and_
+
+class Voter(Module):
+    def __init__(self):
+        self.data_4x = Signal(32)
+        self.k_4x = Signal(4)
+        
+        # Section 9.2.2.1 (CXP-001-2021)
+        # decoder should immune to single bit errors when handling duplicated characters
+        self.char = Signal(8)
+        self.k = Signal()
+
+
+        # majority voting
+        char = [[self.data_4x[i*8:(i+1)*8], self.k_4x[i]] for i in range(4)]
+        voter = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
+
+        # stage 1
+        for i, code in enumerate(combinations(char, 3)):
+            self.sync += [
+                voter[i].data.eq(reduce(and_, [c[0] for c in code])),
+                voter[i].k.eq(reduce(and_, [c[1] for c in code])),
+            ]
+
+        # stage 2
+        self.sync += [
+            self.char.eq(reduce(or_, [v.data for v in voter])),
+            self.k.eq(reduce(or_, [v.k for v in voter])),
+        ]
+
+        
+
+
+dut = Voter()
+def check_case(data_4x, k_4x, char, k):
+  yield dut.data_4x.eq(data_4x)
+  yield dut.k_4x.eq(k_4x)
+  yield
+  yield
+  yield
+  print(f"char = {yield dut.char:#X} k = {yield dut.k:#X}")
+  assert (yield dut.char) == char and (yield dut.k) == k
+
+def testbench():
+  yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
+  yield from check_case(0xFFFFFF00, 0b1110, 0xFF, 1)
+  yield from check_case(0xFFFFF00f, 0b0001, 0xFF, 0)
+  yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
+
+run_simulation(dut, testbench())

sim_arbiter.py

@@ -0,0 +1,125 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from src.gateware.cxp_frame_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+CXP_CHANNELS = 2
+
+class Frame_Pipeline(Module):
+    def __init__(self, n_downconn, n_buffer=2):
+        # to construct correct crc and ack/stb signal
+        self.sinks = []
+        self.downconn_source = []
+        for i in range(n_downconn):
+            # generating the packet
+            buffer = stream.SyncFIFO(word_layout, 32)
+            crc_inserter = CXPCRC32Inserter(False)
+            dchar_decoder = Duplicated_Char_Decoder()
+
+            pipeline = [buffer, crc_inserter, dchar_decoder]
+            self.submodules += pipeline
+
+            for s, d in zip(pipeline, pipeline[1:]):
+                self.comb += s.source.connect(d.sink)
+            self.sinks.append(pipeline[0].sink)
+            self.downconn_source.append(pipeline[-1].source)
+
+
+        self.buffer_sinks = []
+        for i in range(n_buffer):
+            # it should be mem block not "cycle buffer"
+            buf = DChar_Dropper()
+            self.submodules += buf
+            self.sync += buf.source.ack.eq(1) # no backpressure for sim
+
+            self.buffer_sinks.append(buf.sink)
+        
+        self.submodules.router = Frame_Packet_Router(self.downconn_source, self.buffer_sinks,packet_size=16384)
+
+
+
+
+dut = Frame_Pipeline(CXP_CHANNELS)
+
+
+def packet_sim(packets=[], active_ch=2):
+    assert len(packets) == CXP_CHANNELS
+    assert active_ch <= CXP_CHANNELS
+
+    print("=================TEST========================")
+    yield dut.router.active_src_mask.eq(active_ch - 1)
+    sinks = dut.sinks
+
+    cyc = len(packets[0])
+    for c in range(cyc):
+        for i, pak in enumerate(packets):
+            yield sinks[i].data.eq(pak[c]["data"])
+            yield sinks[i].k.eq(pak[c]["k"])
+            yield sinks[i].stb.eq(1)
+            if "eop" in pak[c]:
+                yield sinks[i].eop.eq(1)
+            else:
+                yield sinks[i].eop.eq(0)
+
+        yield
+
+    # extra clk cycles
+    for _ in range(cyc, cyc + 100):
+        for i in range(CXP_CHANNELS):
+            yield sinks[i].data.eq(0)
+            yield sinks[i].k.eq(0)
+            yield sinks[i].stb.eq(0)
+            yield sinks[i].eop.eq(0)
+            yield
+    assert True
+
+
+def testbench(n_downconn):
+    paks = []
+    for i in range(n_downconn):
+        stream_id = i
+
+        frame_packets = [
+            # frame #0
+            [
+                {"data": C((i+1)<< 28 | 0x1111, word_dw), "k": Replicate(1, 4)},
+                {"data": C((i+1)<< 28 | 0x2222, word_dw), "k": Replicate(0, 4)},
+                {"data": C((i+1)<< 28 | 0x3333, word_dw), "k": Replicate(0, 4)},
+                {"data": C((i+1)<< 28 | 0x4444, word_dw), "k": Replicate(0, 4), "eop":0},
+            ],
+            # frame #1
+            [
+                {"data": C((i+1)<< 28 | 0x5555, word_dw), "k": Replicate(1, 4)},
+                {"data": C((i+1)<< 28 | 0x6666, word_dw), "k": Replicate(0, 4)},
+                {"data": C((i+1)<< 28 | 0x7777, word_dw), "k": Replicate(0, 4)},
+                {"data": C((i+1)<< 28 | 0x8888, word_dw), "k": Replicate(0, 4), "eop":0},
+            ],
+        ]
+
+        total_pak = []
+        for frame in frame_packets:
+            total_pak += [
+                {"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
+                {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
+                {
+                    "data": Replicate(C(len(frame), 2 * char_width)[8:], 4),
+                    "k": Replicate(0, 4),
+                },
+                {
+                    "data": Replicate(C(len(frame), 2 * char_width)[:8], 4),
+                    "k": Replicate(0, 4),
+                },
+            ]
+            total_pak += frame
+        
+        paks.append(
+            total_pak
+        )
+
+    yield from packet_sim(paks)
+
+
+run_simulation(dut, testbench(CXP_CHANNELS), vcd_name="sim-cxp.vcd")

sim_broadcaster.py

@@ -0,0 +1,91 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from src.gateware.cxp_frame_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+class double_buffer_pipeline(Module):
+    def __init__(self):
+        fifo = stream.SyncFIFO(word_layout, 32)
+        dchar_decoder = Duplicated_Char_Decoder()
+        broadcaster = Stream_Broadcaster(1)
+        pipeline = [fifo, dchar_decoder, broadcaster]
+        self.submodules += pipeline
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+
+        self.submodules.buffer = buffer = Buffer(word_layout_dchar)
+        self.comb += broadcaster.sources[0].connect(buffer.sink)
+        self.source = buffer.source
+       
+
+        # for sim, no backpressure
+        self.comb += self.source.ack.eq(1)
+
+
+
+dut = double_buffer_pipeline()
+
+
+def packet_sim(packets=[]):
+    print("=================TEST========================")
+    sink = dut.sink
+
+    cyc = len(packets)
+    pak = packets
+    for c in range(cyc):
+        yield sink.data.eq(pak[c]["data"])
+        yield sink.k.eq(pak[c]["k"])
+        yield sink.stb.eq(1)
+        if "eop" in pak[c]:
+            yield sink.eop.eq(1)
+        else:
+            yield sink.eop.eq(0)
+        yield
+
+    # extra clk cycles
+    for _ in range(cyc, cyc + 20):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+    assert True
+
+
+def testbench():
+    paks = [
+        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(4, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(4, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
+        {"data": C(0x7C7C7C7C, word_dw), "k": Replicate(1, 4)},
+        {"data": C(0x01010101, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0xF6ACEF6A, word_dw), "k": Replicate(0, 4)},
+
+
+        {"data": Replicate(C(0, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(1, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(8, 2 * char_width)[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(8, 2 * char_width)[:8], 4), "k": Replicate(0, 4)}, # CRC doesn't count
+        {"data": C(0x19191919, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x09090909, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x90909090, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x985EFDB2, word_dw), "k": Replicate(0, 4)},
+    ]
+    yield from packet_sim(paks)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_comb.py

@@ -0,0 +1,28 @@
+from migen import *
+from misoc.interconnect import stream
+
+class Frame(Module):
+    def __init__(self):
+        self.a = Signal()
+        self.b = Signal()
+        self.comb += [
+            self.a.eq(self.b),
+            # self.b.eq(self.a),
+        ]
+
+dut = Frame()
+
+def check_case():
+    yield dut.a.eq(1)
+    yield 
+    yield dut.a.eq(0)
+    yield 
+    for i in range(10):
+        yield
+
+
+def testbench():
+    yield from check_case()
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_crc.py

@@ -0,0 +1,58 @@
+from migen import *
+from misoc.interconnect import stream
+from sim_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+dut = StreamData_Generator()
+
+
+def check_case(packet=[], ack=0):
+    print("=================TEST========================")
+    for i, p in enumerate(packet):
+        yield dut.sink.data.eq(p["data"])
+        yield dut.sink.k.eq(p["k"])
+        yield dut.sink.stb.eq(1)
+        if "eop" in p:
+            yield dut.sink.eop.eq(1)
+
+        # CLK 
+        yield
+
+        sink = dut.sink
+        source = dut.source
+        crc = dut.crc_inserter.crc
+        print(
+            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
+            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
+            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
+            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
+            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
+        )
+    # extra clk cycles
+    cyc = i + 1
+    for i in range(cyc, cyc + 11):
+        # yield has memory for some reason
+        yield dut.sink.stb.eq(0)
+        yield dut.source.ack.eq(1)
+        yield
+        print(
+            # f"\n CYCLE#{i} : sink char = {yield sink.data:#X} k = {yield sink.k:#X}"
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X}"
+            f" stb = {yield source.stb} eop = {yield source.eop} ack = {yield source.ack} "
+            f"\nCYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
+            f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X}"
+            f"\nCYCLE#{i} : crc ce = {yield crc.ce:#X} "
+        )
+    assert True
+
+
+def testbench():
+    packet = [
+        {"data": 0x0000_0004, "k": Replicate(0, 4)},
+        {"data": 0x0000_0000, "k": Replicate(0, 4), "eop":1},
+    ]
+    yield from check_case(packet)
+
+
+run_simulation(dut, testbench())

sim_double_buffer.py

@@ -0,0 +1,80 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from src.gateware.cxp_frame_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+class double_buffer_pipeline(Module):
+    def __init__(self):
+        fifo = stream.SyncFIFO(word_layout_dchar, 32)
+        double_buffer = Double_Stream_Buffer(0x100)
+        dchar_dropper = DChar_Dropper()
+        pipeline = [fifo, double_buffer, dchar_dropper]
+        self.submodules += pipeline
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # for sim, no backpressure
+        self.comb += self.source.ack.eq(1)
+
+
+
+dut = double_buffer_pipeline()
+
+
+def packet_sim(packets=[]):
+    print("=================TEST========================")
+    sink = dut.sink
+
+    cyc = len(packets)
+    pak = packets
+    for c in range(cyc):
+        yield sink.data.eq(pak[c]["data"])
+        yield sink.k.eq(pak[c]["k"])
+        yield sink.stb.eq(1)
+        if "eop" in pak[c]:
+            yield sink.eop.eq(1)
+        else:
+            yield sink.eop.eq(0)
+        yield
+
+    # extra clk cycles
+    for _ in range(cyc, cyc + 20):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+    assert True
+
+
+def testbench():
+    paks = [
+        {"data": C(0x7C7C7C7C, word_dw), "k": Replicate(1, 4)},
+        {"data": C(0x01010101, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        # {"data": C(0xF6ACEF6B, word_dw), "k": Replicate(0, 4), "eop":1},
+        {"data": C(0x6AEFACF6, word_dw), "k": Replicate(0, 4), "eop":1},
+
+
+        {"data": C(0x19191919, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x09090909, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x90909090, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x00000000, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0xB2FD5E98, word_dw), "k": Replicate(0, 4), "eop":1},
+    ]
+    yield from packet_sim(paks)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_eop.py

@@ -0,0 +1,72 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from src.gateware.cxp_frame_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+class EOP_Pipeline(Module):
+    def __init__(self):
+        dchar_decoder = Duplicated_Char_Decoder()
+        eop_inserter = EOP_Inserter()
+        buffer = stream.SyncFIFO(word_layout_dchar, 32)
+        pipeline = [dchar_decoder, eop_inserter, buffer]
+        self.submodules += pipeline
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # for sim, no backpressure
+        self.comb += self.source.ack.eq(1)
+
+
+
+dut = EOP_Pipeline()
+
+
+def packet_sim(packets=[]):
+    print("=================TEST========================")
+    sink = dut.sink
+
+    cyc = len(packets)
+    pak = packets
+    for c in range(cyc):
+        yield sink.data.eq(pak[c]["data"])
+        yield sink.k.eq(pak[c]["k"])
+        yield sink.stb.eq(1)
+        yield
+
+    # extra clk cycles
+    for _ in range(cyc, cyc + 10):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+    assert True
+
+
+def testbench():
+    paks = [
+        {"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
+        {"data": C(0x1111, word_dw), "k": Replicate(1, 4)},
+        {"data": C(0x2222, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x3333, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0x4444, word_dw), "k": Replicate(0, 4)},
+        {"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
+
+        {"data": Replicate(KCode["pak_start"], 4), "k": Replicate(1, 4)},
+        {"data": C(0xAAAA, word_dw), "k": Replicate(1, 4)},
+        {"data": C(0xBBBB, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0xCCCC, word_dw), "k": Replicate(0, 4)},
+        {"data": C(0xDDDD, word_dw), "k": Replicate(0, 4)},
+        {"data": Replicate(KCode["pak_end"], 4), "k": Replicate(1, 4)},
+    ]
+    yield from packet_sim(paks)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_frame.py

@@ -0,0 +1,134 @@
+from migen import *
+from misoc.interconnect import stream
+
+from sim_generator import CXPCRC32Inserter
+from sim_frame_gen import get_frame_packet
+
+from src.gateware.cxp_pipeline import *
+from src.gateware.cxp_frame_pipeline import *
+
+import numpy as np
+from PIL import Image
+
+
+class Frame(Module):
+    def __init__(self):
+        # to construct correct crc and ack/stb signal
+        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
+        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
+        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
+
+        # NOTE: eop is needed for crc to work correctly and RX_Bootstrap need to be followed by a EOP marker anyway
+        self.submodules.eop_marker = eop_marker = EOP_Marker()
+
+        self.submodules.stream_pipe = stream_pipe = Stream_Pipeline()
+
+        pipeline = [buffer, crc_inserter, dchar_decoder, eop_marker, stream_pipe]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # no backpressure for sim
+        self.sync += self.source.ack.eq(1)
+
+
+dut = Frame()
+
+
+def check_case(packet=[]):
+    print("=================TEST========================")
+
+    sink = dut.sink
+    stream_pipe = dut.stream_pipe
+
+    for i, p in enumerate(packet):
+        yield sink.data.eq(p["data"])
+        yield sink.k.eq(p["k"])
+        yield sink.stb.eq(1)
+        if "eop" in p:
+            yield sink.eop.eq(1)
+        else:
+            yield sink.eop.eq(0)
+
+        # check cycle result
+        yield
+        # source = dut.dchar_decoder.source
+        # source = dut.stream_pipe.frame_extractor.sink
+        source = dut.sink
+        # print(
+        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+        # )
+
+    # extra clk cycles
+    cyc = i + 1
+    img = []
+    line = -1
+    total_pixel = 1000
+    for i in range(cyc, cyc + total_pixel):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+        # print(
+        #     f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+        # )
+
+        frame_extractoer = dut.stream_pipe.frame_extractor
+        new_line = yield frame_extractoer.new_line
+        if new_line:
+            img.append([])
+            line += 1
+            
+        stb = yield frame_extractoer.source.stb 
+        data = yield frame_extractoer.source.data
+        if stb:
+            # CXP use MSB
+            img[line].append(np.uint16(data & 0xFFFF))
+            img[line].append(np.uint16(data >> 16))
+
+        # metadata = dut.stream_pipe.frame_extractor.metadata
+        # img_header_layout = [
+        #     "stream_id",
+        #     "source_tag",
+        #     "x_size",
+        #     "x_offset",
+        #     "y_size",
+        #     "y_offset",
+        #     "l_size",  # number of data words per image line
+        #     "pixel_format",
+        #     "tap_geo",
+        #     "flag",
+        # ]
+        # for name in img_header_layout:
+        #     print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
+        # print()
+    Image.fromarray(np.array(img, dtype=np.uint8)).show()
+    assert True
+
+
+def testbench():
+    stream_id = 0x69
+    packet_tag = 0
+    frame_packet = get_frame_packet(stream_id)
+    packet = [
+        {"data": Replicate(C(stream_id, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(C(packet_tag, char_width), 4), "k": Replicate(0, 4)},
+        {
+            "data": Replicate(C(len(frame_packet), 2*char_width)[8:], 4),
+            "k": Replicate(0, 4),
+        },
+        {
+            "data": Replicate(C(len(frame_packet), 2*char_width)[:8], 4),
+            "k": Replicate(0, 4),
+        },
+    ]
+    packet += frame_packet
+    # NOTE: for crc inserter!!!!
+    packet[-1]["eop"] = 0
+
+    yield from check_case(packet)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_frame_gen.py

@@ -0,0 +1,148 @@
+from migen import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_pipeline import *
+from src.gateware.cxp_frame_pipeline import *
+
+from PIL import Image
+import numpy as np
+
+
+def get_image_header(
+    stream_id, source_tag, xsize, xoffset, ysize, yoffset, dsize, pixelF, tag_geo, flag
+):
+    stream_id = C(stream_id, char_width)
+    source_tag = C(source_tag, 2 * char_width)
+    xsize = C(xsize, 3 * char_width)
+    xoffset = C(xoffset, 3 * char_width)
+    ysize = C(ysize, 3 * char_width)
+    yoffset = C(yoffset, 3 * char_width)
+    dsize = C(dsize, 3 * char_width)
+    pixelF = C(pixelF, 2 * char_width)
+    tag_geo = C(tag_geo, 2 * char_width)
+    flag = C(flag, char_width)
+
+    assert len(stream_id) == len(flag) == char_width
+    assert len(source_tag) == len(pixelF) == len(tag_geo) == 2 * char_width
+    assert len(xsize) == len(xoffset) == len(ysize) == len(yoffset) == 3 * char_width
+    return [
+        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
+        {"data": Replicate(C(0x01, char_width), 4), "k": Replicate(0, 4)},
+        {"data": Replicate(stream_id, 4), "k": Replicate(0, 4)},
+        {"data": Replicate(source_tag[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(source_tag[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xsize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(xoffset[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(ysize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(yoffset[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[16:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[8:16], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(dsize[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(pixelF[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(pixelF[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(tag_geo[8:], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(tag_geo[:8], 4), "k": Replicate(0, 4)},
+        {"data": Replicate(flag, 4), "k": Replicate(0, 4)},
+    ]
+
+
+def get_line_marker():
+    return [
+        {"data": Replicate(KCode["stream_marker"], 4), "k": Replicate(1, 4)},
+        {"data": Replicate(C(0x02, char_width), 4), "k": Replicate(0, 4)},
+    ]
+
+
+def get_frame_packet(stream_id, pixel_format="mono16"):
+    assert pixel_format in ["mono16"]
+
+    arr = [
+        [204, 200, 203, 205, 190, 187, 189, 205, 214, 197, 188, 185, 181, 178, 193, 209, 211, 207, 211, 192, 168, 168, 171, 199, 210, 212, 203, 196],
+        [218, 205, 199, 190, 192, 197, 196, 195, 184, 178, 182, 173, 166, 132, 122, 114, 154, 184, 187, 188, 171, 168, 170, 180, 192, 196, 202, 198],
+        [223, 222, 222, 224, 216, 199, 199, 207, 205, 189, 183, 182, 144, 66,  61,  66, 80, 148, 181, 175, 169, 170, 174, 177, 196, 206, 223, 218],
+        [221, 226, 225, 222, 211, 200, 202, 208, 215, 201, 187, 180, 133, 116, 113, 118, 96, 111, 206, 193, 170, 169, 186, 211, 218, 224, 231, 223],
+        [219, 216, 206, 197, 210, 201, 206, 203, 191, 190, 185, 145, 134, 140, 159, 170, 150, 116, 180, 173, 179, 170, 172, 185, 201, 218, 227, 227],
+        [203, 198, 194, 208, 227, 201, 201, 201, 215, 221, 209, 170, 136, 113, 141, 139, 141, 145, 188, 170, 180, 169, 184, 173, 174, 192, 215, 230],
+        [206, 224, 213, 213, 233, 207, 204, 226, 233, 227, 214, 166, 145, 123, 145, 155, 147, 186, 213, 187, 171, 169, 193, 193, 171, 178, 186, 207],
+        [212, 228, 216, 205, 214, 205, 204, 230, 235, 225, 219, 187, 143, 122, 146, 163, 158, 195, 209, 203, 174, 168, 190, 185, 187, 202, 180, 174],
+        [197, 206, 201, 223, 213, 201, 203, 231, 234, 225, 218, 206, 147, 125, 149, 155, 190, 208, 206, 203, 175, 168, 171, 179, 184, 206, 189, 176],
+        [213, 202, 209, 235, 223, 200, 202, 202, 227, 227, 202, 176, 138, 122, 144, 153, 190, 209, 207, 191, 172, 167, 179, 204, 190, 191, 180, 193],
+        [225, 225, 207, 231, 219, 197, 215, 200, 194, 199, 181, 172, 131, 129, 147, 159, 113, 175, 196, 179, 184, 169, 181, 210, 202, 204, 200, 177],
+        [208, 222, 204, 223, 210, 191, 195, 198, 203, 167, 171, 168, 135, 129, 149, 175,  66,  57,  90, 121, 147, 165, 181, 205, 195, 217, 209, 173],
+        [188, 216, 201, 206, 199, 180, 185, 180, 129,  75, 139, 166, 124, 146, 189, 135,  51,  41,  38,  40,  45,  63, 131, 201, 189, 215, 193, 170],
+        [188, 194, 195, 192, 182, 180, 134,  68,  45,  41,  96, 130, 116, 156, 163,  64,  46,  41,  43,  41,  42,  42,  74, 181, 177, 198, 175, 193],
+        [179, 179, 209, 224, 198, 182,  99,  42,  44,  41,  44, 100, 116, 125, 100,  46,  45,  42,  42,  37,  44,  43,  49, 150, 183, 170, 172, 198],
+        [175, 177, 208, 223, 197, 180,  94,  40,  42,  40,  41,  99, 134, 117,  80,  43,  46,  43,  37,  37,  44,  42,  35, 129, 195, 170, 170, 180],
+        [179, 181, 187, 217, 193, 175,  91,  38,  41,  41,  42, 106, 151, 107,  62,  43,  45,  41,  33,  38,  42,  34,  33,  77, 188, 175, 173, 208],
+        [190, 191, 180, 213, 194, 175,  78,  38,  40,  40,  40,  98, 134, 97,  51,  44,  59,  50,  37,  40,  36,  26,  36,  44, 100, 178, 192, 206],
+        [199, 191, 184, 204, 196, 176,  78,  33,  38,  38,  39,  80, 102, 83,  43,  44, 112, 130, 122,  63,  33,  24,  29,  34,  33,  74, 162, 195],
+        [191, 170, 196, 193, 186, 177,  88,  27,  34,  37,  36,  74, 101, 70,  36,  37,  81, 127, 137, 113,  40,  28,  30,  32,  36,  29, 69, 173],
+        [164, 189, 190, 180, 176, 172,  83,  26,  28,  33,  32,  68,  97, 62,  32,  30,  44,  97, 123, 136,  58,  42,  44,  43,  43,  40, 58, 162],
+        [177, 202, 205, 181, 174, 163,  78,  38,  35,  47,  54,  67,  92, 51,  28,  29,  26,  21,  39,  85,  47,  46,  52,  47,  46,  45, 48, 141],
+        [181, 193, 199, 192, 171, 163,  91,  67, 121, 123,  91,  63,  89, 45,  25,  25,  23,  20,  15,  13,  20,  48,  54,  35,  34,  34, 68, 146],
+        [175, 192, 195, 179, 165, 163, 100,  64,  99,  94,  82,  58,  83, 37,  23,  22,  22,  27,  21,  15,  14,  44,  98,  83,  94, 118, 164, 157],
+        [153, 184, 171, 163, 161, 157, 140,  70,  58,  89,  61,  53,  76, 30,  20,  20,  20,  31,  24,  19,  16,  47, 159, 163, 160, 171, 160, 142],
+        [142, 150, 161, 168, 154, 154, 164, 138,  76,  55,  26,  37,  62, 24,  19,  19,  20,  21,  23,  27,  31,  46, 142, 156, 151, 153, 147, 145],
+        [153, 147, 174, 171, 151, 150, 169, 158, 142,  92,  28,  60,  59, 20,  20,  18,  20,  26,  27,  29,  33,  38, 125, 153, 150, 147, 147, 148],
+        [138, 141, 166, 164, 146, 144, 164, 149, 132,  72,  34,  88,  72, 24,  19,  18,  18,  23,  25,  28,  31,  30,  98, 150, 146, 144, 146, 144]
+    ]
+    source_tag = 0
+    xsize, ysize = len(arr[0]), len(arr)
+
+    xoffset, yoffset = 0, 0
+    if pixel_format == "mono16":
+        dsize = xsize // 2
+        pixelF = 0x0105
+    tag_geo = 0
+    flag = 0
+
+    packet = []
+    # Image header
+    packet += get_image_header(
+        stream_id,
+        source_tag,
+        xsize,
+        xoffset,
+        ysize,
+        yoffset,
+        dsize,
+        pixelF,
+        tag_geo,
+        flag,
+    )
+
+    for line in arr:
+        packet += get_line_marker()
+        if pixel_format == "mono16":
+            for i in range(len(line)):
+                if (i % 2) == 0:
+                    if i == len(line) - 1:
+                        # print(C(line[i]))
+                        packet += [
+                            {
+                                "data": C(line[i], 4 * char_width),
+                                "k": Replicate(0, 4),
+                            },
+                        ]
+                    else:
+                        # print(C(line[i], 2 * char_width), C(line[i + 1]))
+                        # CXP use MSB
+                        packet += [
+                            {
+                                "data": Cat(
+                                    C(line[i], 2 * char_width),
+                                    C(line[i + 1], 2 * char_width),
+                                ),
+                                "k": Replicate(0, 4),
+                            },
+                        ]
+
+    return packet

sim_generator.py

@@ -0,0 +1,122 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_frame_pipeline import CXPCRC32
+from src.gateware.cxp_pipeline import *
+
+class CXPCRC32Inserter(Module):
+    def __init__(self, insert_eop=True):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.crc = crc = CXPCRC32(word_dw)
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        # WARNING: this will eat data if the source don't care about ack
+        # NOTE: need one cycle to turn itself on
+        fsm.act(
+            "IDLE",
+            crc.reset.eq(1),
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("COPY"),
+            ),
+        )
+        fsm.act(
+            "COPY",
+            crc.ce.eq(self.sink.stb & self.source.ack),
+            crc.data.eq(self.sink.data),
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(
+                self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT"),
+            ),
+        )
+        fsm.act(
+            "INSERT",
+            self.source.stb.eq(1),
+            self.source.eop.eq(1) if insert_eop else self.source.eop.eq(0),
+            self.source.data.eq(crc.value),
+            If(self.source.ack, NextState("IDLE")),
+        )
+
+
+class StreamPacket_Wrapper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act(
+            "IDLE",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT_HEADER_0"),
+            ),
+        )
+
+        fsm.act(
+            "INSERT_HEADER_0",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("INSERT_HEADER_1")),
+        )
+
+        fsm.act(
+            "INSERT_HEADER_1",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+        fsm.act(
+            "COPY",
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(
+                self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT_FOOTER"),
+            ),
+        )
+
+        fsm.act(
+            "INSERT_FOOTER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            # Simulate RX don't have eop tagged
+            # self.source.eop.eq(1),
+            If(self.source.ack, NextState("IDLE")),
+        )
+
+
+# With KCode & 0x01*4
+class StreamData_Generator(Module):
+    def __init__(self):
+        # should be big enough for all test
+        self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
+        self.submodules.crc_inserter = crc_inserter = CXPCRC32Inserter()
+        self.submodules.wrapper = wrapper = StreamPacket_Wrapper()
+
+        # # #
+        pipeline = [buffer, crc_inserter, wrapper]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source

sim_idle.py

@@ -0,0 +1,149 @@
+from migen import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_pipeline import Packet_Wrapper
+
+char_width = 8
+word_dw = 32
+word_layout = [("data", word_dw), ("k", word_dw//8)]
+
+
+def K(x, y):
+    return ((y << 5) | x)
+
+KCode = {
+    "pak_start" : C(K(27, 7), char_width),
+    "io_ack" : C(K(28, 6), char_width), 
+    "trig_indic_28_2" : C(K(28, 2), char_width),
+    "stream_marker" : C(K(28, 3), char_width),
+    "trig_indic_28_4" : C(K(28, 4), char_width),
+    "pak_end" : C(K(29, 7), char_width),
+    "idle_comma" : C(K(28, 5), char_width),
+    "idle_alignment" : C(K(28, 1), char_width),
+}
+
+class TX_Bootstrap(Module):
+    def __init__(self):
+        self.tx_testseq = Signal()
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.source = stream.Endpoint(word_layout)
+
+        self.cnt = Signal(max=0xFFF)
+        fsm.act("IDLE",
+            If(self.tx_testseq, 
+                NextValue(self.cnt, self.cnt.reset),
+                NextState("WRITE_TEST_PACKET_TYPE"),
+            )
+        )
+
+        fsm.act("WRITE_TEST_PACKET_TYPE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
+        )
+
+        # testword = Signal(word_dw)
+        # self.comb += [
+        #     testword[:8].eq(self.cnt[:8]),
+        #     testword[8:16].eq(self.cnt[:8]+1),
+        #     testword[16:24].eq(self.cnt[:8]+2),
+        #     testword[24:].eq(self.cnt[:8]+3),
+        # ]
+
+        fsm.act("WRITE_TEST_COUNTER",
+            self.source.stb.eq(1),
+            self.source.data[:8].eq(self.cnt[:8]),
+            self.source.data[8:16].eq(self.cnt[:8]+1),
+            self.source.data[16:24].eq(self.cnt[:8]+2),
+            self.source.data[24:].eq(self.cnt[:8]+3),
+            self.source.k.eq(Cat(0, 0, 0, 0)),
+            If(self.source.ack,
+                If(self.cnt == 0x0FF-3,
+                    self.source.eop.eq(1),
+                    NextState("IDLE")
+                ).Else(
+                    NextValue(self.cnt, self.cnt + 4),
+                )
+               
+            )
+        )
+
+class Idle_Word_Inserter(Module):
+    def __init__(self):
+        # Section 9.2.5 (CXP-001-2021)
+        # Send K28.5, K28.1, K28.1, D21.5  as idle word
+        self.submodules.fsm = fsm = FSM(reset_state="WRITE_IDLE")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        cnt = Signal(max=0x10, reset=0xF)
+        
+        fsm.act("WRITE_IDLE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
+            self.source.k.eq(Cat(1, 1, 1, 0)),
+
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                If(self.source.ack,
+                    NextValue(cnt, cnt.reset),
+                    NextState("COPY"),
+                )
+            ),
+        )
+
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            # increment when upstream has data and got ack
+            If(self.sink.stb & self.source.ack, NextValue(cnt, cnt - 1)),
+            If((((~self.sink.stb) | (self.sink.eop) | (cnt == 0) ) & self.source.ack), NextState("WRITE_IDLE"))
+        )
+
+class Pipeline(Module):
+    def __init__(self):
+        self.submodules.bootstrap = boostrap = TX_Bootstrap()
+        self.submodules.wrapper = wrapper = Packet_Wrapper()
+        # self.submodules.buffer = buffer = stream.SyncFIFO(word_layout, 32)
+        self.submodules.idle_inserter = idle_inserter = Idle_Word_Inserter()
+
+        # # #
+
+        pipeline = [boostrap, wrapper, idle_inserter]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        # self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # no backpressure
+        # self.comb += self.source.ack.eq(1)
+
+dut = Pipeline()
+
+def check_case():
+    source = dut.source
+    # sink = dut.sink
+    # for i in range(1, 30):
+    #     yield sink.data.eq(i)
+    #     yield sink.stb.eq(1)
+    #     yield 
+    yield dut.bootstrap.tx_testseq.eq(1)
+    yield
+    yield dut.bootstrap.tx_testseq.eq(0)
+    for i in range(10):
+        yield
+    for _ in range(100):
+        yield source.ack.eq(1)
+        yield
+
+
+def testbench():
+    yield from check_case()
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_roi.py

@@ -0,0 +1,230 @@
+from migen import *
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from src.gateware.cxp_frame_pipeline import *
+from src.gateware.cxp_pipeline import *
+
+class ROI(Module):
+    def __init__(self):
+        fifo = stream.SyncFIFO(word_layout, 32) # to avoid data getting eaten and act as delay between eop
+        dchar_decoder = Duplicated_Char_Decoder()
+        # self.crc = CXPCRC32_Checker()
+        self.pipeline = ROI_Pipeline()
+
+        pipeline = [fifo, dchar_decoder, self.pipeline]
+        self.submodules += pipeline
+
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+
+
+dut = ROI()
+
+
+def packet_sim(packets=[]):
+    print("=================TEST========================")
+    sink = dut.sink
+
+    cyc = len(packets)
+    pak = packets
+    for c in range(cyc):
+        yield sink.data.eq(pak[c]["data"])
+        yield sink.k.eq(pak[c]["k"])
+        yield sink.stb.eq(1)
+        if "eop" in pak[c]:
+            yield sink.eop.eq(1)
+        else:
+            yield sink.eop.eq(0)
+        yield
+
+    # extra clk cycles
+    for _ in range(cyc, cyc + 20):
+        yield sink.data.eq(0)
+        yield sink.k.eq(0)
+        yield sink.stb.eq(0)
+        yield sink.eop.eq(0)
+        yield
+    metadata = dut.pipeline.header_decoder.metadata
+    img_header_layout = [
+        "stream_id",
+        "source_tag", # image index since powering on
+        "x_size",
+        "x_offset",
+        "y_size",
+        "y_offset",
+        "l_size",  # number of data words per image line
+        "pixel_format",
+        "tap_geo",
+        "flag",
+    ]
+    for name in img_header_layout:
+        print(f"{name} = {yield getattr(metadata, name):#04X} ", end="")
+    print()
+    assert True
+
+
+def testbench():
+    paks = [
+        {"data": C(0x7C7C7C7C, word_dw), "k" : Replicate(1, 4)}, 
+        {"data": C(0x01010101, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, # stream id
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x6AEFACF6, word_dw), "k" : Replicate(0, 4), "eop":0}, # crc
+
+        {"data": C(0x02020202, word_dw), "k" : Replicate(0, 4)},  
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, # Xsize[23:16]
+        {"data": C(0x09090909, word_dw), "k" : Replicate(0, 4)}, # Xsize[15:8] 
+        {"data": C(0x90909090, word_dw), "k" : Replicate(0, 4)}, # Xsize[7:0] 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x8EE1DAA1, word_dw), "k" : Replicate(0, 4), "eop":0}, # crc
+
+        {"data": C(0x08080808, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x08080808, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, # DsizeL[23:16] 
+        {"data": C(0x02020202, word_dw), "k" : Replicate(0, 4)}, # DsizeL[15:8] 
+        {"data": C(0x64646464, word_dw), "k" : Replicate(0, 4)}, # DsizeL[7:0] 
+        {"data": C(0x01010101, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x01010101, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x00000000, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x51C243EA, word_dw), "k" : Replicate(0, 4), "eop":0}, # crc
+
+        # the new line + pixel data
+        {"data": C(0x7C7C7C7C, word_dw), "k" : Replicate(1, 4)}, 
+        {"data": C(0x02020202, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0D0D0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0B0D, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0D0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0A0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0C0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0D0A, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0A0B0D, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0D0C0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0A0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0D0D0B0A, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0C0B0B0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0C0C0B, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0x0B0B0B0C, word_dw), "k" : Replicate(0, 4)}, 
+        {"data": C(0xCB5DCDD6, word_dw), "k" : Replicate(0, 4), "eop": 0}, # crc
+
+        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0B0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0B0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0D0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0A, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0D0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0D, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0A0C0C0D, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0B0A, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0B0D0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0D0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0B0A, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0A0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0D0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0D0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0D0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0D0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0C0D0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0D0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0D0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0B0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0B0C0B, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0B0C0C0D, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0D0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0B0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0C0C0C0C, word_dw), "k" : Replicate(0, 4)},  
+        # {"data": C(0x0BADF020, word_dw), "k" : Replicate(0, 4), "eop":0},  # crc
+    ]
+    yield from packet_sim(paks)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

sim_stream.py

@@ -0,0 +1,154 @@
+from migen import *
+from misoc.interconnect import stream
+
+from sim_pipeline import *
+from sim_generator import StreamData_Generator
+
+from src.gateware.cxp_pipeline import *
+
+class CXP_Links(Module):
+    def __init__(self):
+        # TODO: select the correct buffer to read from
+        # NOTE: although there are double buffer in each connect, the reading must be faster than writing to avoid data loss
+
+        self.downconn_sources = []
+        self.stream_sinks = []
+        for i in range(2):
+            downconn = Pipeline()
+            setattr(self.submodules, "cxp_conn"+str(i), downconn)
+            self.downconn_sources.append(downconn)
+
+            stream_pipeline = Stream_Pipeline()
+            setattr(self.submodules, "stream_pipeline"+str(i), stream_pipeline)
+            self.stream_sinks.append(stream_pipeline)
+
+        self.submodules.crossbar = Streams_Crossbar(self.downconn_sources, self.stream_sinks)
+        
+class Pipeline(Module):
+    def __init__(self):
+        self.submodules.generator = generator = StreamData_Generator()
+        self.submodules.dchar_decoder = dchar_decoder = Duplicated_Char_Decoder()
+        self.submodules.data_decoder = data_decoder = RX_Bootstrap()
+        self.submodules.eop_marker = eop_marker = EOP_Marker()
+
+        # # #
+
+        pipeline = [generator, dchar_decoder, data_decoder, eop_marker]
+        for s, d in zip(pipeline, pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = pipeline[0].sink
+        self.source = pipeline[-1].source
+
+        # self.comb += self.source.ack.eq(1)
+
+
+dut = CXP_Links()
+
+def check_case(packet=[]):
+    print("=================TEST========================")
+
+    downconns = dut.downconn_sources
+    stream_buffers = dut.stream_sinks
+    ch = 0
+    
+    for i, p in enumerate(packet):
+        for x in range(len(downconns)):
+            if x == ch:
+                yield downconns[x].sink.data.eq(p["data"])
+                yield downconns[x].sink.k.eq(p["k"])
+                yield downconns[x].sink.stb.eq(1)
+            else:
+                yield downconns[x].sink.data.eq(0)
+                yield downconns[x].sink.k.eq(0)
+                yield downconns[x].sink.stb.eq(0)
+                yield downconns[x].sink.eop.eq(0)
+        if "eop" in p:
+            yield downconns[ch].sink.eop.eq(1)
+            # compensate for delay
+            # yield
+            # yield downconns[ch].sink.data.eq(0)
+            # yield downconns[ch].sink.k.eq(0)
+            # yield downconns[ch].sink.stb.eq(0)
+            # yield downconns[ch].sink.eop.eq(0)
+            # yield
+            # yield
+            # yield
+            ch = (ch + 1) % len(downconns)
+        else:
+            yield downconns[ch].sink.eop.eq(0)
+
+        # check cycle result
+        yield
+        # source = dut.stream_pipeline_sinks[0].source
+        source = dut.stream_sinks[0].double_buffer.source
+        print(
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
+            f"\nCYCLE#{i} : read mask = {yield dut.crossbar.mux.sel}"
+            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
+            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
+        )
+        # crc = downconns[1].generator.crc_inserter.crc
+        # crc = dut.double_buffer.crc
+        # print(
+        #     f"CYCLE#{i} : crc error = {yield crc.error:#X} crc value = {yield crc.value:#X}"
+        #     f" crc data = {yield crc.data:#X} engine next = {yield crc.engine.next:#X} ce = {yield crc.ce}"
+        # )
+
+            
+    # extra clk cycles
+    cyc = i + 1
+    for i in range(cyc, cyc + 30):
+        for x in range(len(downconns)):
+            # yield won't reset every cycle
+            yield downconns[x].sink.data.eq(0)
+            yield downconns[x].sink.k.eq(0)
+            yield downconns[x].sink.stb.eq(0)
+            yield downconns[x].sink.eop.eq(0)
+        yield
+        print(
+            f"\nCYCLE#{i} : source char = {yield source.data:#X} k = {yield source.k:#X} stb = {yield source.stb} ack = {yield source.ack} eop = {yield source.eop}"
+            # f" source dchar = {yield source.dchar:#X} dchar_k = {yield source.dchar_k:#X}"
+            f"\nCYCLE#{i} : read mask = {yield dut.crossbar .mux.sel}"
+            # f"\nCYCLE#{i} : stream id = {yield decoder.stream_id:#X} pak_tag = {yield decoder.pak_tag:#X}"
+            # f" stream_pak_size = {yield decoder.stream_pak_size:#X}"
+        )
+    assert True
+
+
+def testbench():
+    # stream_id = 0x01
+    streams = [
+        [
+            {"data": 0x11111111, "k": Replicate(0, 4)},
+            {"data": 0xB105F00D, "k": Replicate(0, 4)},
+        ],
+        [
+            {"data": 0x22222222, "k": Replicate(0, 4)},
+            {"data": 0xC001BEA0, "k": Replicate(0, 4)},
+        ],
+        [
+            {"data": 0x33333333, "k": Replicate(0, 4)},
+            {"data": 0xC0A79AE5, "k": Replicate(0, 4)},
+        ],
+    ]
+
+    packet = []
+    for i, s in enumerate(streams):
+        s[-1]["eop"] = 0
+        packet += [
+            {"data": Replicate(C(i % 2, char_width), 4), "k": Replicate(0, 4)},
+            {"data": Replicate(C(i, char_width), 4), "k": Replicate(0, 4)},
+            {
+                "data": Replicate(C(len(s) >> 8 & 0xFF, char_width), 4),
+                "k": Replicate(0, 4),
+            },
+            {"data": Replicate(C(len(s) & 0xFF, char_width), 4), "k": Replicate(0, 4)},
+            *s,
+        ]
+
+
+    yield from check_case(packet)
+
+
+run_simulation(dut, testbench(), vcd_name="sim-cxp.vcd")

src/Cargo.lock

@@ -278,6 +278,7 @@ name = "libboard_artiq"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
+ "byteorder",
  "core_io",
  "crc",
  "embedded-hal",
@@ -559,9 +560,7 @@ name = "satman"
 version = "0.0.0"
 dependencies = [
  "build_zynq",
- "byteorder",
  "core_io",
- "crc",
  "cslice",
  "embedded-hal",
  "io",

src/gateware/cxp.py

@@ -0,0 +1,356 @@
+from migen import *
+from migen.genlib.cdc import MultiReg, PulseSynchronizer, BusSynchronizer
+from misoc.interconnect.csr import *
+
+from artiq.gateware.rtio import rtlink
+
+from cxp_downconn import CXP_DownConn_PHYS
+from cxp_upconn import CXP_UpConn_PHYS
+from cxp_pipeline import *
+from cxp_frame_pipeline import *
+
+from functools import reduce
+from operator import add
+
+class CXP_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, upconn_pads, downconn_pads, sys_clk_freq, debug_sma, pmod_pads):
+        assert len(upconn_pads) == len(downconn_pads)
+
+        self.submodules.upconn = CXP_UpConn_PHYS(upconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+        self.submodules.downconn = CXP_DownConn_PHYS(refclk, downconn_pads, sys_clk_freq, debug_sma, pmod_pads)
+
+@FullMemoryWE()
+class CXP_Interface(Module, AutoCSR):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        self.submodules.upconn = UpConn_Interface(upconn_phy, debug_sma, pmod_pads)
+        self.submodules.downconn = DownConn_Interface(downconn_phy, debug_sma, pmod_pads)
+
+    def get_tx_port(self):
+        return self.upconn.bootstrap.mem.get_port(write_capable=True)
+
+    def get_tx_mem_size(self):
+        # FIXME: if tx mem size is NOT same as rx, for some reason when rx mem is writen, tx mem cannot be access anymore
+        # and each time tx mem is read, CPU will return rx mem instead (fixed by reordering the mem allocation order)
+        # FIXME: seems like there are address alignment issue, if tx mem size is 0x800, the mem following the tx mem cannot be read correctly
+        # However, if tx mem is 0x2000 (same size as rx mem) the following rx mem can be read correctly
+        return self.upconn.bootstrap.mem.depth*self.upconn.bootstrap.mem.width // 8 # 0x800
+        # return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8 # 0x2000
+
+    def get_mem_size(self):
+        return word_dw * buffer_count * buffer_depth // 8
+
+    def get_rx_port(self):
+        return self.downconn.bootstrap.mem.get_port(write_capable=False)
+
+    def get_rx_mem_size(self):
+        return self.downconn.bootstrap.mem.depth*self.downconn.bootstrap.mem.width // 8
+
+    def get_rx_downconn(self):
+        return self.downconn
+
+class CXP_Master(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+        nbit_trigdelay = 8
+        nbit_linktrig = 1
+
+        self.rtlink = rtlink.Interface(
+            rtlink.OInterface(nbit_trigdelay + nbit_linktrig),
+            rtlink.IInterface(word_dw, timestamped=False)
+        )
+
+        self.sync.rio += [
+            If(self.rtlink.o.stb,
+                self.upconn.trig.delay.eq(self.rtlink.o.data[nbit_linktrig:]),
+                self.upconn.trig.linktrig_mode.eq(self.rtlink.o.data[:nbit_linktrig]),
+            ),
+            self.upconn.trig.stb.eq(self.rtlink.o.stb),
+        ]
+
+        # DEBUG: out
+        self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.p_tx),
+        # self.specials += Instance("OBUF", i_I=self.rtlink.o.stb, o_O=debug_sma.n_rx),
+
+class CXP_Extension(CXP_Interface):
+    def __init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads):
+        CXP_Interface.__init__(self, upconn_phy, downconn_phy, debug_sma, pmod_pads)
+
+
+class DownConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        self.rx_ready = CSRStatus()
+
+        # # #
+
+        gtx = phy.gtx
+
+        # GTX status
+        self.sync += self.rx_ready.status.eq(gtx.rx_ready)
+
+        # DEBUG: init status
+        self.txinit_phaligndone = CSRStatus()
+        self.rxinit_phaligndone = CSRStatus()
+        self.comb += [
+            self.txinit_phaligndone.status.eq(gtx.tx_init.Xxphaligndone),
+            self.rxinit_phaligndone.status.eq(gtx.rx_init.Xxphaligndone),
+        ]
+
+        # Connect all GTX connections' DRP
+        self.gtx_daddr = CSRStorage(9)
+        self.gtx_dread = CSR()
+        self.gtx_din_stb = CSR()
+        self.gtx_din = CSRStorage(16)
+
+        self.gtx_dout = CSRStatus(16)
+        self.gtx_dready = CSR()
+
+        self.comb += gtx.dclk.eq(ClockSignal("sys"))
+        self.sync += [
+            gtx.daddr.eq(self.gtx_daddr.storage),
+            gtx.den.eq(self.gtx_dread.re | self.gtx_din_stb.re),
+            gtx.dwen.eq(self.gtx_din_stb.re),
+            gtx.din.eq(self.gtx_din.storage),
+            If(gtx.dready,
+                self.gtx_dready.w.eq(1),
+                self.gtx_dout.status.eq(gtx.dout),
+            ).Elif(self.gtx_dready.re,
+                self.gtx_dready.w.eq(0),
+            ),
+        ]
+
+
+        # Receiver Pipeline WIP
+        # 
+        #        32             32+8(dchar)
+        # PHY ---/---> dchar   -----/-----> trigger ack ------>  packet  ------> CDC FIFO ------> debug buffer
+        #              decoder              checker              decoder
+        #
+        cdr = ClockDomainsRenamer("cxp_gtx_rx")
+
+        # decode all incoming data as duplicate char and inject the result into the bus for downstream modules
+        self.submodules.dchar_decoder = dchar_decoder = cdr(Duplicated_Char_Decoder())
+
+        # Priority level 1 packet - Trigger ack packet
+        self.submodules.trig_ack_checker = trig_ack_checker = cdr(Trigger_Ack_Checker())
+        
+        self.submodules.trig_ack_ps = trig_ack_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.sync.cxp_gtx_rx += trig_ack_ps.i.eq(trig_ack_checker.ack)
+
+        self.trig_ack = Signal()
+        self.trig_clr = Signal()
+        # Error are latched
+        self.sync += [
+            If(trig_ack_ps.o,
+                self.trig_ack.eq(1),
+            ).Elif(self.trig_clr,
+                self.trig_ack.eq(0),
+            ),
+        ]
+
+        # Priority level 2 packet - data, test packet
+        self.submodules.bootstrap = bootstrap = cdr(RX_Bootstrap())
+
+        self.bootstrap_decoder_err = CSR()
+        self.bootstrap_buffer_err = CSR()
+
+        decode_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        buffer_err_ps = PulseSynchronizer("cxp_gtx_rx", "sys")
+        self.submodules += decode_err_ps, buffer_err_ps
+        self.sync.cxp_gtx_rx += [
+            decode_err_ps.i.eq(bootstrap.decode_err),
+            buffer_err_ps.i.eq(bootstrap.buffer_err),
+        ]
+        self.sync += [
+            If(decode_err_ps.o,
+                self.bootstrap_decoder_err.w.eq(1),
+            ).Elif(self.bootstrap_decoder_err.re,
+                self.bootstrap_decoder_err.w.eq(0),
+            ),
+            If(buffer_err_ps.o,
+                self.bootstrap_buffer_err.w.eq(1),
+            ).Elif(self.bootstrap_buffer_err.re,
+                self.bootstrap_buffer_err.w.eq(0),
+            ),
+        ]
+
+        
+        # test packet error & packet counters
+        self.bootstrap_test_error_counter = CSRStatus(len(bootstrap.test_err_cnt))
+        self.bootstrap_test_packet_counter = CSRStatus(len(bootstrap.test_pak_cnt))
+        self.bootstrap_test_counts_reset = CSR()
+
+
+        test_reset_ps = PulseSynchronizer("sys", "cxp_gtx_rx")
+        self.submodules += test_reset_ps
+        self.sync += test_reset_ps.i.eq(self.bootstrap_test_counts_reset.re),
+
+        test_err_cnt_r = Signal.like(bootstrap.test_err_cnt)
+        test_pak_cnt_r = Signal.like(bootstrap.test_pak_cnt)
+        self.sync.cxp_gtx_rx += [ 
+            bootstrap.test_cnt_reset.eq(test_reset_ps.o),
+            test_err_cnt_r.eq(bootstrap.test_err_cnt),
+            test_pak_cnt_r.eq(bootstrap.test_pak_cnt),
+        ]
+        self.specials += [
+            MultiReg(test_err_cnt_r, self.bootstrap_test_error_counter.status),
+            MultiReg(test_pak_cnt_r, self.bootstrap_test_packet_counter.status),
+        ]
+
+        # Cicular buffer interface
+        self.packet_type = CSRStatus(8)
+        self.pending_packet = CSR()
+        self.read_ptr = CSRStatus(log2_int(buffer_count))
+
+        self.specials += [
+            MultiReg(bootstrap.packet_type, self.packet_type.status),
+            MultiReg(self.read_ptr.status, bootstrap.read_ptr_rx, odomain="cxp_gtx_rx"),
+        ]
+        self.sync += [
+            self.pending_packet.w.eq(self.read_ptr.status != bootstrap.write_ptr_sys),
+            If(~gtx.rx_ready,
+                self.read_ptr.status.eq(0),
+            ).Elif(self.pending_packet.re & self.pending_packet.w, 
+                self.read_ptr.status.eq(self.read_ptr.status + 1),
+            )
+        ]
+        
+        # DEBUG: 
+        # # add buffer to improve timing & reduce tight setup/hold time
+        # self.submodules.buffer_cdc_fifo = buffer_cdc_fifo = cdr(Buffer(word_layout_dchar))
+        # cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 512)
+        # self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+        # self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar)
+
+        rx_pipeline = [phy, dchar_decoder, trig_ack_checker, bootstrap]
+        for s, d in zip(rx_pipeline, rx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.source = rx_pipeline[-1].source
+        
+
+        # DEBUG: CSR
+        self.trigger_ack = CSR()
+        self.sync += [
+            self.trig_clr.eq(self.trigger_ack.re),
+            self.trigger_ack.w.eq(self.trig_ack),
+        ]
+
+
+        
+class UpConn_Interface(Module, AutoCSR):
+    def __init__(self, phy, debug_sma, pmod_pads):
+        # Transmission Pipeline
+        #
+        #              32                                                  32           8
+        # ctrl/test ---/---> packet -----> idle word -----> trigger ack ---/--> conv ---/---> trigger -----> PHY
+        # packet             wrapper       inserter         inserter                          inserter
+        #
+        # Equivalent transmission priority:
+        # trigger > trigger ack > idle > test/data packet
+        # To maintain the trigger performance, idle word should not be inserted into trigger or trigger ack.
+        # 
+        # In low speed CoaXpress, the higher priority packet can be inserted in two types of boundary
+        # Insertion @ char boundary: Trigger packets
+        # Insertion @ word boundary: Trigger ack & IDLE packets
+        # The 32 bit part of the pipeline handles the word boundary insertion while the 8 bit part handles the char boundary insertion
+        
+
+
+        # Packet FIFOs with transmission priority
+        # 0: Trigger packet
+        self.submodules.trig = trig = TX_Trigger()
+        
+        # # DEBUG: INPUT
+        self.trig_stb = CSR()
+        self.trig_delay = CSRStorage(8) 
+        self.linktrigger = CSRStorage()
+
+        # self.sync += [
+        #     trig.stb.eq(self.trig_stb.re),
+        #     trig.delay.eq(self.trig_delay.storage),
+        #     trig.linktrig_mode.eq(self.linktrigger.storage),
+        # ]
+
+        
+        # 1: IO acknowledgment for trigger packet
+        self.submodules.trig_ack = trig_ack = Trigger_ACK_Inserter()
+
+        # DEBUG: INPUT
+        self.ack = CSR()
+        self.sync += trig_ack.stb.eq(self.ack.re),
+
+
+        # 2: All other packets (data & test packet)
+        # Control is not timing dependent, all the data packets are handled in firmware
+        self.submodules.bootstrap = bootstrap = TX_Bootstrap()
+
+        self.submodules.pak_wrp = pak_wrp = Packet_Wrapper()
+        self.submodules.idle = idle = Idle_Word_Inserter()
+
+        self.submodules.converter = converter = stream.StrideConverter(word_layout, char_layout)
+
+        tx_pipeline = [bootstrap, pak_wrp, idle, trig_ack, converter, trig, phy]
+        for s, d in zip(tx_pipeline, tx_pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+
+class CXP_Frame_Pipeline(Module, AutoCSR):
+    # optimal stream packet size is 2 KiB - Section 9.5.2 (CXP-001-2021)
+    def __init__(self, downconns, pmod_pads, packet_size=16384, n_buffer=1):
+        n_downconn = len(downconns)
+        
+        framebuffers = []
+        arr_csr = []
+        cdr = ClockDomainsRenamer("cxp_gtx_rx")
+        for i in range(n_buffer):
+            # TODO: change this to rtio
+            if i > 0:
+                name = "buffer_" + str(i) + "_routingid"
+                csr = CSRStorage(char_width, name=name, reset=i)
+                arr_csr.append(csr)
+                setattr(self, name, csr)
+
+            roi_pipeline = ROI_Pipeline()
+            self.submodules += roi_pipeline
+            framebuffers.append(roi_pipeline.pipeline[0])
+
+            # DEBUG:
+            # self.comb += roi_pipeline.pipeline[-1].source.ack.eq(1)
+
+
+            # crc_checker = cdr(CXPCRC32_Checker())
+
+            # # TODO: handle full buffer gracefully
+            # # TODO: investigate why there is a heartbeat message in the middle of the frame with k27.7 code too???
+            # # NOTE: sometimes there are 0xFBFBFBFB K=0b1111
+            # # perhaps the buffer is full overflowing and doing strange stuff             
+
+            # # it should be mem block not "cycle buffer"
+            # # self.submodules.dropper = dropper = cdr(DChar_Dropper())
+            # buffer_cdc_fifo = cdr(Buffer(word_layout_dchar)) # to improve timing
+            # cdc_fifo = stream.AsyncFIFO(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+            # self.submodules += crc_checker, buffer_cdc_fifo
+            # self.submodules += ClockDomainsRenamer({"write": "cxp_gtx_rx", "read": "sys"})(cdc_fifo)
+
+            # pipeline = [crc_checker, buffer_cdc_fifo, cdc_fifo]
+            # for s, d in zip(pipeline, pipeline[1:]):
+            #     self.comb += s.source.connect(d.sink)
+            # framebuffers.append(pipeline[0])
+            
+
+            # # DEBUG:
+            # if i == 0:
+            #     self.submodules.debug_out = debug_out = RX_Debug_Buffer(word_layout_dchar, 2**log2_int(packet_size//word_dw))
+            #     self.comb += pipeline[-1].source.connect(debug_out.sink)
+            # else:
+            #     # remove any backpressure 
+            #     self.comb += pipeline[-1].source.ack.eq(1)
+
+
+        self.submodules.router = router = cdr(Frame_Packet_Router(downconns, framebuffers, packet_size, pmod_pads))
+
+        for i, csr in enumerate(arr_csr):
+            self.specials += MultiReg(csr.storage, router.routing_table[i], odomain="cxp_gtx_rx"),
+
+        # only the simple topology MASTER:ch0, extension:ch1,2,3 is supported right now
+        active_extensions = Signal(max=n_downconn)
+        self.sync += active_extensions.eq(reduce(add, [d.rx_ready.status for d in downconns[1:]]))
+        self.specials += MultiReg(active_extensions, router.n_ext_active, odomain="cxp_gtx_rx"),

src/gateware/cxp_4r_fmc.py

@@ -0,0 +1,87 @@
+from migen.build.generic_platform import *
+
+fmc_adapter_io = [
+
+    # CoaXPress high speed link
+    ("CXP_HS", 0,
+        Subsignal("txp", Pins("HPC:DP0_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP0_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP0_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP0_M2C_N")),
+    ),
+    ("CXP_HS", 1,
+        Subsignal("txp", Pins("HPC:DP1_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP1_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP1_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP1_M2C_N")),
+    ),
+    ("CXP_HS", 2,
+        Subsignal("txp", Pins("HPC:DP2_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP2_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP2_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP2_M2C_N")),
+    ),
+    ("CXP_HS", 3,
+        Subsignal("txp", Pins("HPC:DP3_C2M_P")),
+        Subsignal("txn", Pins("HPC:DP3_C2M_N")),
+        Subsignal("rxp", Pins("HPC:DP3_M2C_P")),
+        Subsignal("rxn", Pins("HPC:DP3_M2C_N")),
+    ),
+
+    # CoaXPress low speed link
+    ("CXP_LS", 0, Pins("HPC:LA00_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 1, Pins("HPC:LA01_CC_N"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 2, Pins("HPC:LA01_CC_P"), IOStandard("LVCMOS33")),
+    ("CXP_LS", 3, Pins("HPC:LA02_N"), IOStandard("LVCMOS33")),
+
+    # CoaXPress green and red LED
+    ("CXP_LED", 0,
+        Subsignal("green", Pins("HPC:LA11_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA11_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 1,
+        Subsignal("green", Pins("HPC:LA12_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA12_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 2,
+        Subsignal("green", Pins("HPC:LA13_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA13_N"), IOStandard("LVCMOS33")),
+    ),
+    ("CXP_LED", 3,
+        Subsignal("green", Pins("HPC:LA14_P"), IOStandard("LVCMOS33")),
+        Subsignal("red", Pins("HPC:LA14_N"), IOStandard("LVCMOS33")),
+    ),
+
+    # Power over CoaXPress 
+    ("PoCXP", 0,
+        Subsignal("enable", Pins("HPC:LA21_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA18_CC_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 1,
+        Subsignal("enable", Pins("HPC:LA21_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_N"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 2,
+        Subsignal("enable", Pins("HPC:LA22_N"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA19_P"), IOStandard("LVCMOS33")),
+    ),
+    ("PoCXP", 3,
+        Subsignal("enable", Pins("HPC:LA22_P"), IOStandard("LVCMOS33")),
+        Subsignal("alert", Pins("HPC:LA20_N"), IOStandard("LVCMOS33")),
+    ),
+
+    ("i2c_fmc", 0,
+        Subsignal("scl", Pins("HPC:IIC_SCL")),
+        Subsignal("sda", Pins("HPC:IIC_SDA")),
+        IOStandard("LVCMOS33")
+    ),
+
+    ("3V3", 0, Pins("HPC:PG_M2C")),
+    ("GND", 0, Pins("HPC:PRSNT_M2C_L HPC:CLK0_M2C_P")),
+    ("VADJ", 0, Pins("HPC:GBTCLK1_M2C_N CLK0_M2C_N")),
+
+    ("clk125_fmc", 0,
+        Subsignal("p", Pins("HPC:GBTCLK0_M2C_P")),
+        Subsignal("n", Pins("HPC:GBTCLK0_M2C_n")),
+    ),
+]

src/gateware/cxp_downconn.py

@@ -0,0 +1,644 @@
+from migen import *
+from migen.genlib.cdc import MultiReg
+from migen.genlib.resetsync import AsyncResetSynchronizer
+
+from misoc.cores.code_8b10b import Encoder, Decoder
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from artiq.gateware.drtio.transceiver.gtx_7series_init import *
+from cxp_pipeline import word_layout
+
+from functools import reduce
+from operator import add
+
+class CXP_DownConn_PHYS(Module, AutoCSR):
+    def __init__(self, refclk, pads, sys_clk_freq, debug_sma, pmod_pads, master=0):
+        self.qpll_reset = CSR()
+        self.qpll_locked = CSRStatus()
+        self.gtx_start_init = CSRStorage()
+        self.gtx_restart = CSR()
+
+        self.rx_phys = []
+        # # #
+
+        # For speed higher than 6.6Gbps, QPLL need to be used instead of CPLL
+        self.submodules.qpll = qpll = QPLL(refclk, sys_clk_freq)
+        self.sync += [
+            qpll.reset.eq(self.qpll_reset.re),
+            self.qpll_locked.status.eq(qpll.lock),
+        ]
+
+        self.submodules.rx_resetter = rx_resetter = RX_Resetter()
+
+        for i, pad in enumerate(pads):
+            if len(pads) == 1:
+                rx_mode = "single"
+            else:
+                rx_mode = "master" if i == master else "slave"
+            rx = Receiver(qpll, pad, sys_clk_freq, "single", rx_mode, debug_sma, pmod_pads)
+            self.rx_phys.append(rx)
+            setattr(self.submodules, "rx"+str(i), rx)
+
+        for i, phy in enumerate(self.rx_phys):
+            if i == master:
+                self.comb += rx_resetter.rx_ready.eq(phy.gtx.rx_ready)
+            self.comb += [
+                phy.gtx.rx_manual_restart.eq(self.gtx_restart.re | rx_resetter.rx_reset),
+                phy.gtx.rx_init.clk_path_ready.eq(self.gtx_start_init.storage),
+            ]
+
+        # master rx_init will lock up when slaves_phaligndone signal is not connected
+        self.submodules.rx_phase_alignment = GTXInitPhaseAlignment([rx_phy.gtx.rx_init for rx_phy in self.rx_phys])
+
+class Receiver(Module):
+    def __init__(self, qpll, pad, sys_clk_freq, tx_mode, rx_mode, debug_sma, pmod_pads):
+        self.submodules.gtx = gtx = GTX(qpll, pad, sys_clk_freq, tx_mode, rx_mode)
+       
+        self.source = stream.Endpoint(word_layout)
+
+        data_valid = Signal()
+        self.sync.cxp_gtx_rx += [
+            data_valid.eq(gtx.comma_aligner.rxfsm.ongoing("READY")),
+
+            self.source.stb.eq(0),
+            If(data_valid & self.source.ack & ~((gtx.decoders[0].d == 0xBC) & (gtx.decoders[0].k == 1)),
+                self.source.stb.eq(1),
+                self.source.data.eq(Cat(gtx.decoders[i].d for i in range(4))),
+                self.source.k.eq(Cat(gtx.decoders[i].k for i in range(4))),
+            )
+        ]
+
+class QPLL(Module, AutoCSR):
+    def __init__(self, refclk, sys_clk_freq):
+        self.clk = Signal()
+        self.refclk = Signal()
+        self.lock = Signal()
+        self.reset = Signal()
+
+        self.daddr = CSRStorage(8)
+        self.dread = CSR()
+        self.din_stb = CSR()
+        self.din = CSRStorage(16)
+
+        self.dout = CSRStatus(16)
+        self.dready = CSR()
+
+        # # #
+
+        # VCO @ 10GHz, linerate = 1.25Gbps
+        # feedback divider = 80
+        qpll_fbdiv = 0b0100100000
+        qpll_fbdiv_ratio = 1
+        refclk_div = 1
+        self.Xxout_div = 8
+
+        # used for txuserclk pll
+        fbdiv_real = 80
+        self.tx_usrclk_freq = (sys_clk_freq*fbdiv_real/self.Xxout_div)/40
+        
+        dready = Signal()
+        self.specials += [
+            Instance("GTXE2_COMMON",
+                i_QPLLREFCLKSEL=0b001,
+                i_GTREFCLK0=refclk,         
+
+                i_QPLLPD=0,
+                i_QPLLRESET=self.reset,
+                i_QPLLLOCKEN=1,
+                o_QPLLLOCK=self.lock,
+                o_QPLLOUTCLK=self.clk,
+                o_QPLLOUTREFCLK=self.refclk,
+
+                # See UG476 (v1.12.1) Table 2-16
+                p_QPLL_FBDIV=qpll_fbdiv,
+                p_QPLL_FBDIV_RATIO=qpll_fbdiv_ratio,
+                p_QPLL_REFCLK_DIV=refclk_div,
+
+                # From 7 Series FPGAs Transceivers Wizard
+                p_BIAS_CFG=0x0000040000001000,
+                p_COMMON_CFG=0x00000000,
+                p_QPLL_CFG=0x0680181,
+                p_QPLL_CLKOUT_CFG=0b0000,
+                p_QPLL_COARSE_FREQ_OVRD=0b010000,
+                p_QPLL_COARSE_FREQ_OVRD_EN=0b0,
+                p_QPLL_CP=0b0000011111,
+                p_QPLL_CP_MONITOR_EN=0b0,
+                p_QPLL_DMONITOR_SEL=0b0,
+                p_QPLL_FBDIV_MONITOR_EN= 0b0,
+                p_QPLL_INIT_CFG=0x000006,
+                p_QPLL_LOCK_CFG=0x21E8,
+                p_QPLL_LPF=0b1111,
+             
+                # Reserved, values cannot be modified
+                i_BGBYPASSB=0b1,
+                i_BGMONITORENB=0b1,
+                i_BGPDB=0b1,
+                i_BGRCALOVRD=0b11111,
+                i_RCALENB=0b1,
+                i_QPLLRSVD1=0b0,
+                i_QPLLRSVD2=0b11111,
+
+                # Dynamic Reconfiguration Ports
+                i_DRPADDR=self.daddr.storage,
+                i_DRPCLK=ClockSignal("sys"),
+                i_DRPEN=(self.dread.re | self.din_stb.re),
+                i_DRPWE=self.din_stb.re,
+                i_DRPDI=self.din.storage,
+                o_DRPDO=self.dout.status,
+                o_DRPRDY=dready,
+            )
+        ]
+
+        self.sync += [
+            If(dready,
+               self.dready.w.eq(1),
+            ),
+            If(self.dready.re,
+               self.dready.w.eq(0),
+            ),
+        ]
+
+
+class RX_Resetter(Module):
+    def __init__(self, reset_period=10_000_000):
+        self.rx_ready = Signal()
+        self.rx_reset = Signal()
+
+        # # #
+
+        # periodically reset rx until rx is connected and receiving valid data
+        # as after connecting RXP/RXN, the whole RX need to be reset 
+        
+        reset_counter = Signal(reset=reset_period-1, max=reset_period)
+        self.sync += [
+            self.rx_reset.eq(0),
+            If(~self.rx_ready,
+                If(reset_counter == 0,
+                    reset_counter.eq(reset_counter.reset),
+                    self.rx_reset.eq(1),
+                ).Else(
+                    reset_counter.eq(reset_counter - 1),
+                )
+            )
+        ]
+
+# Warning: Xilinx transceivers are LSB first, and comma needs to be flipped
+# compared to the usual 8b10b binary representation.
+class Comma_Aligner(Module):
+    def __init__(self, comma, reset_period=10_000_000):
+        self.data = Signal(20)
+        self.comma_aligned = Signal()
+        self.comma_realigned = Signal()
+        self.comma_det = Signal()
+
+        self.aligner_en = Signal()
+        self.ready_sys = Signal()
+
+        # # #
+
+        # Data and comma checker
+        # From UG476 (v1.12.1) p.228
+        # The built-in RXBYTEISALIGNED can be falsely asserted at linerate higher than 5Gbps
+        # The validity of data and comma needed to be checked externally
+
+        comma_n = ~comma & 0b1111111111
+
+        comma_seen = Signal()
+        error_seen = Signal()
+        one_counts = Signal(max=11)
+
+        # From CXP-001-2021 section 9.2.5.1
+        # For high speed connection an IDLE word shall be transmitted at least once every 100 words
+        counter_period = 200
+
+        counter = Signal(reset=counter_period-1, max=counter_period)
+        check_reset = Signal()
+        check = Signal()
+
+        self.sync.cxp_gtx_rx += [
+            If(check_reset,
+                counter.eq(counter.reset),   
+                check.eq(0),
+            ).Elif(counter == 0,
+                check.eq(1),
+            ).Else(
+                counter.eq(counter - 1),   
+            ),
+
+            If(check_reset,
+                comma_seen.eq(0),
+            ).Elif((self.data[:10] == comma) | (self.data[:10] == comma_n),
+                comma_seen.eq(1)
+            ),
+
+            one_counts.eq(reduce(add, [self.data[i] for i in range(10)])),
+            If(check_reset,
+                error_seen.eq(0),
+            ).Elif((one_counts != 4) & (one_counts != 5) & (one_counts != 6),
+                error_seen.eq(1),
+            ),
+
+        ]
+
+        self.submodules.rxfsm = rxfsm = ClockDomainsRenamer("cxp_gtx_rx")(FSM(reset_state="WAIT_COMMA"))
+
+        rxfsm.act("WAIT_COMMA",
+            If(self.comma_det,
+                NextState("ALIGNING"),
+            )
+        )
+
+        rxfsm.act("ALIGNING",
+            If(self.comma_aligned & (~self.comma_realigned),
+                NextState("WAIT_ALIGNED_DATA"),               
+            ).Else(
+                self.aligner_en.eq(1),
+            )
+        )
+
+        # wait for the aligned data to arrive at the FPGA RX interface 
+        # as there is a delay before the data is avaiable after RXBYTEISALIGNED is asserted
+        self.submodules.timer = timer = ClockDomainsRenamer("cxp_gtx_rx")(WaitTimer(10_000))
+
+        rxfsm.act("WAIT_ALIGNED_DATA",
+            timer.wait.eq(1),
+            If(timer.done,
+                check_reset.eq(1),
+                NextState("CHECKING"),
+            )
+        )
+
+        rxfsm.act("CHECKING",
+            If(check,
+                check_reset.eq(1),
+                If(comma_seen & (~error_seen),
+                    NextState("READY"),
+                ).Else(
+                    NextState("WAIT_COMMA")
+                )
+            )
+        )
+
+        ready = Signal()
+        self.specials += MultiReg(ready, self.ready_sys)
+        rxfsm.act("READY",
+            ready.eq(1),
+            If(check,
+                check_reset.eq(1),
+                If(~(comma_seen & (~error_seen)),
+                    NextState("WAIT_COMMA"),
+                )
+            )
+        )
+
+
+class GTX(Module):
+    def __init__(self, qpll, pads, sys_clk_freq, tx_mode="single", rx_mode="single"):
+        assert tx_mode in ["single", "master", "slave"]
+        assert rx_mode in ["single", "master", "slave"]
+
+        # linerate = USRCLK * datawidth
+        pll_fbout_mult = 8
+        txusr_pll_div = pll_fbout_mult*sys_clk_freq/qpll.tx_usrclk_freq
+
+        self.tx_restart = Signal()
+        self.rx_manual_restart = Signal()
+        self.loopback_mode = Signal(3)
+
+        self.txenable = Signal()
+        self.rx_ready = Signal()
+
+        # Dynamic Reconfiguration Ports
+        self.daddr = Signal(9)
+        self.dclk = Signal()
+        self.den = Signal()
+        self.dwen = Signal()
+        self.din = Signal(16)
+        self.dout = Signal(16)
+        self.dready = Signal()
+
+        self.submodules.encoder = ClockDomainsRenamer("cxp_gtx_tx")(Encoder(4, True))
+        self.submodules.decoders = [ClockDomainsRenamer("cxp_gtx_rx")(
+            (Decoder(True))) for _ in range(4)]
+
+
+        # transceiver direct clock outputs
+        # useful to specify clock constraints in a way palatable to Vivado
+        self.txoutclk = Signal()
+        self.rxoutclk = Signal()
+
+        # # #
+
+        # TX generates cxp_tx clock, init must be in system domain
+        self.submodules.tx_init = tx_init = GTXInit(sys_clk_freq, False, mode=tx_mode)
+        self.submodules.rx_init = rx_init = GTXInit(sys_clk_freq, True, mode=rx_mode)
+
+        self.comb += [
+            tx_init.cplllock.eq(qpll.lock),
+            rx_init.cplllock.eq(qpll.lock)
+        ]
+
+        txdata = Signal(40)
+        rxdata = Signal(40)
+
+        comma_aligned = Signal()
+        comma_realigned = Signal()
+        comma_det = Signal()
+        comma_aligner_en = Signal()
+        # Note: the following parameters were set after consulting AR45360
+        self.specials += \
+            Instance("GTXE2_CHANNEL",
+                # PMA Attributes
+                p_PMA_RSV=0x001E7080,
+                p_PMA_RSV2=0x2050,              # PMA_RSV2[5] = 0: Eye scan feature disabled
+                p_PMA_RSV3=0,
+                p_PMA_RSV4=1,                   # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                p_RX_BIAS_CFG=0b000000000100,
+                p_RX_OS_CFG=0b0000010000000,
+                p_RX_CLK25_DIV=5,
+                p_TX_CLK25_DIV=5,
+
+                # Power-Down Attributes
+                p_PD_TRANS_TIME_FROM_P2=0x3c,
+                p_PD_TRANS_TIME_NONE_P2=0x3c,
+                p_PD_TRANS_TIME_TO_P2=0x64,
+                i_CPLLPD=1,
+
+                # QPLL
+                i_QPLLCLK=qpll.clk,
+                i_QPLLREFCLK=qpll.refclk,
+                p_RXOUT_DIV=qpll.Xxout_div,
+                p_TXOUT_DIV=qpll.Xxout_div,
+                i_RXSYSCLKSEL=0b11, # use QPLL & QPLL's REFCLK
+                i_TXSYSCLKSEL=0b11, # use QPLL & CPLL's REFCLK
+
+                # TX clock
+                p_TXBUF_EN="FALSE",
+                p_TX_XCLK_SEL="TXUSR",
+                o_TXOUTCLK=self.txoutclk,
+                # i_TXSYSCLKSEL=0b00,
+                i_TXOUTCLKSEL=0b11,
+
+                # TX Startup/Reset
+                i_TXPHDLYRESET=0,
+                i_TXDLYBYPASS=0,
+                i_TXPHALIGNEN=1 if tx_mode != "single" else 0,
+                i_GTTXRESET=tx_init.gtXxreset,
+                o_TXRESETDONE=tx_init.Xxresetdone,
+                i_TXDLYSRESET=tx_init.Xxdlysreset,
+                o_TXDLYSRESETDONE=tx_init.Xxdlysresetdone,
+                i_TXPHINIT=tx_init.txphinit if tx_mode != "single" else 0,
+                o_TXPHINITDONE=tx_init.txphinitdone if tx_mode != "single" else Signal(),
+                i_TXPHALIGN=tx_init.Xxphalign if tx_mode != "single" else 0,
+                i_TXDLYEN=tx_init.Xxdlyen if tx_mode != "single" else 0,
+                o_TXPHALIGNDONE=tx_init.Xxphaligndone,
+                i_TXUSERRDY=tx_init.Xxuserrdy,
+                p_TXPMARESET_TIME=1,
+                p_TXPCSRESET_TIME=1,
+                i_TXINHIBIT=~self.txenable,
+
+                # TX data
+                p_TX_DATA_WIDTH=40,
+                p_TX_INT_DATAWIDTH=1, # 1 if a line rate is greater than 6.6 Gbps
+                i_TXCHARDISPMODE=Cat(txdata[9], txdata[19], txdata[29], txdata[39]),
+                i_TXCHARDISPVAL=Cat(txdata[8], txdata[18], txdata[28], txdata[38]),
+                i_TXDATA=Cat(txdata[:8], txdata[10:18], txdata[20:28], txdata[30:38]),
+                i_TXUSRCLK=ClockSignal("cxp_gtx_tx"),
+                i_TXUSRCLK2=ClockSignal("cxp_gtx_tx"),
+
+                # TX electrical
+                i_TXBUFDIFFCTRL=0b100,
+                i_TXDIFFCTRL=0b1000,
+
+                # RX Startup/Reset
+                i_RXPHDLYRESET=0,
+                i_RXDLYBYPASS=0,
+                i_RXPHALIGNEN=1 if rx_mode != "single" else 0,
+                i_GTRXRESET=rx_init.gtXxreset,
+                o_RXRESETDONE=rx_init.Xxresetdone,
+                i_RXDLYSRESET=rx_init.Xxdlysreset,
+                o_RXDLYSRESETDONE=rx_init.Xxdlysresetdone,
+                i_RXPHALIGN=rx_init.Xxphalign if rx_mode != "single" else 0,
+                i_RXDLYEN=rx_init.Xxdlyen if rx_mode != "single" else 0,
+                o_RXPHALIGNDONE=rx_init.Xxphaligndone,
+                i_RXUSERRDY=rx_init.Xxuserrdy,
+                p_RXPMARESET_TIME=1,
+                p_RXPCSRESET_TIME=1,
+
+                # RX AFE
+                p_RX_DFE_XYD_CFG=0,
+                p_RX_CM_SEL=0b11,               # RX_CM_SEL = 0b11: Common mode is programmable
+                p_RX_CM_TRIM=0b010,             # PMA_RSV[4],RX_CM_TRIM[2:0] = 0b1010: Common mode 800mV
+                i_RXDFEXYDEN=1,
+                i_RXDFEXYDHOLD=0,
+                i_RXDFEXYDOVRDEN=0,
+                i_RXLPMEN=1,                    # RXLPMEN = 1: LPM mode is enable for non scramble 8b10b data
+                p_RXLPM_HF_CFG=0b00000011110000,
+                p_RXLPM_LF_CFG=0b00000011110000,
+
+                p_RX_DFE_GAIN_CFG=0x0207EA,
+                p_RX_DFE_VP_CFG=0b00011111100000011,
+                p_RX_DFE_UT_CFG=0b10001000000000000,
+                p_RX_DFE_KL_CFG=0b0000011111110,
+                p_RX_DFE_KL_CFG2=0x3788140A,
+                p_RX_DFE_H2_CFG=0b000110000000,
+                p_RX_DFE_H3_CFG=0b000110000000,
+                p_RX_DFE_H4_CFG=0b00011100000,
+                p_RX_DFE_H5_CFG=0b00011100000,
+                p_RX_DFE_LPM_CFG=0x0904,        # RX_DFE_LPM_CFG = 0x0904: linerate <= 6.6Gb/s
+                                                #                = 0x0104: linerate > 6.6Gb/s
+
+                # RX clock
+                i_RXDDIEN=1,
+                # i_RXSYSCLKSEL=0b00,
+                i_RXOUTCLKSEL=0b010,
+                o_RXOUTCLK=self.rxoutclk,
+                i_RXUSRCLK=ClockSignal("cxp_gtx_rx"),
+                i_RXUSRCLK2=ClockSignal("cxp_gtx_rx"),
+
+                # RX Clock Correction Attributes
+                p_CLK_CORRECT_USE="FALSE",
+                p_CLK_COR_SEQ_1_1=0b0100000000,
+                p_CLK_COR_SEQ_2_1=0b0100000000,
+                p_CLK_COR_SEQ_1_ENABLE=0b1111,
+                p_CLK_COR_SEQ_2_ENABLE=0b1111,
+
+                # RX data
+                p_RX_DATA_WIDTH=40,
+                p_RX_INT_DATAWIDTH=1,   # 1 if a line rate is greater than 6.6 Gbps
+                o_RXDISPERR=Cat(rxdata[9], rxdata[19], rxdata[29], rxdata[39]),
+                o_RXCHARISK=Cat(rxdata[8], rxdata[18], rxdata[28], rxdata[38]),
+                o_RXDATA=Cat(rxdata[:8], rxdata[10:18], rxdata[20:28], rxdata[30:38]),
+
+                # RX Byte and Word Alignment Attributes
+                p_ALIGN_COMMA_DOUBLE="FALSE",
+                p_ALIGN_COMMA_ENABLE=0b1111111111,
+                p_ALIGN_COMMA_WORD=4, # align comma to rxdata[:10] only
+                p_ALIGN_MCOMMA_DET="TRUE",
+                p_ALIGN_MCOMMA_VALUE=0b1010000011,
+                p_ALIGN_PCOMMA_DET="TRUE",
+                p_ALIGN_PCOMMA_VALUE=0b0101111100,
+                p_SHOW_REALIGN_COMMA="FALSE",
+                p_RXSLIDE_AUTO_WAIT=7,
+                p_RXSLIDE_MODE="OFF",
+                p_RX_SIG_VALID_DLY=10,
+                i_RXPCOMMAALIGNEN=comma_aligner_en,
+                i_RXMCOMMAALIGNEN=comma_aligner_en,
+                i_RXCOMMADETEN=1,
+                i_RXSLIDE=0,
+                o_RXBYTEISALIGNED=comma_aligned,
+                o_RXBYTEREALIGN=comma_realigned,
+                o_RXCOMMADET=comma_det,
+
+                # RX 8B/10B Decoder Attributes
+                p_RX_DISPERR_SEQ_MATCH="FALSE",
+                p_DEC_MCOMMA_DETECT="TRUE",
+                p_DEC_PCOMMA_DETECT="TRUE",
+                p_DEC_VALID_COMMA_ONLY="FALSE",
+
+                # RX Buffer Attributes
+                p_RXBUF_ADDR_MODE="FAST",
+                p_RXBUF_EIDLE_HI_CNT=0b1000,
+                p_RXBUF_EIDLE_LO_CNT=0b0000,
+                p_RXBUF_EN="FALSE",
+                p_RX_BUFFER_CFG=0b000000,
+                p_RXBUF_RESET_ON_CB_CHANGE="TRUE",
+                p_RXBUF_RESET_ON_COMMAALIGN="FALSE",
+                p_RXBUF_RESET_ON_EIDLE="FALSE",     # RXBUF_RESET_ON_EIDLE = FALSE: OOB is disabled
+                p_RXBUF_RESET_ON_RATE_CHANGE="TRUE",
+                p_RXBUFRESET_TIME=0b00001,
+                p_RXBUF_THRESH_OVFLW=61,
+                p_RXBUF_THRESH_OVRD="FALSE",
+                p_RXBUF_THRESH_UNDFLW=4,
+                p_RXDLY_CFG=0x001F,
+                p_RXDLY_LCFG=0x030,
+                p_RXDLY_TAP_CFG=0x0000,
+                p_RXPH_CFG=0xC00002,
+                p_RXPHDLY_CFG=0x084020,
+                p_RXPH_MONITOR_SEL=0b00000,
+                p_RX_XCLK_SEL="RXUSR",
+                p_RX_DDI_SEL=0b000000,
+                p_RX_DEFER_RESET_BUF_EN="TRUE",
+
+                # CDR Attributes
+                p_RXCDR_CFG=0x03_0000_23FF_1008_0020,   # LPM @ 0.5G-1.5625G , 8B/10B encoded data, CDR setting < +/- 200ppm
+                                                        # (See UG476 (v1.12.1), p.206)
+                p_RXCDR_FR_RESET_ON_EIDLE=0b0,
+                p_RXCDR_HOLD_DURING_EIDLE=0b0,
+                p_RXCDR_PH_RESET_ON_EIDLE=0b0,
+                p_RXCDR_LOCK_CFG=0b010101,
+
+                # Pads
+                i_GTXRXP=pads.rxp,
+                i_GTXRXN=pads.rxn,
+                o_GTXTXP=pads.txp,
+                o_GTXTXN=pads.txn,
+
+                # Dynamic Reconfiguration Ports
+                p_IS_DRPCLK_INVERTED=0b0,
+                i_DRPADDR=self.daddr,
+                i_DRPCLK=self.dclk,
+                i_DRPEN=self.den,
+                i_DRPWE=self.dwen,
+                i_DRPDI=self.din,
+                o_DRPDO=self.dout,
+                o_DRPRDY=self.dready,
+
+                # ! loopback for debugging
+                i_LOOPBACK = self.loopback_mode,
+                p_TX_LOOPBACK_DRIVE_HIZ = "FALSE",
+                p_RXPRBS_ERR_LOOPBACK = 0b0,
+
+                # Other parameters
+                p_PCS_RSVD_ATTR=(
+                    (tx_mode != "single") << 1 |    # PCS_RSVD_ATTR[1] = 0: TX Single Lane Auto Mode
+                                                    #                  = 1: TX Manual Mode
+                    (rx_mode != "single") << 2 |    #              [2] = 0: RX Single Lane Auto Mode
+                                                    #                  = 1: RX Manual Mode
+                    0 << 8                          #              [8] = 0: OOB is disabled
+                ),
+                i_RXELECIDLEMODE=0b11,              # RXELECIDLEMODE = 0b11: OOB is disabled
+                p_RX_DFE_LPM_HOLD_DURING_EIDLE=0b0,
+                p_ES_EYE_SCAN_EN="TRUE",            # Must be TRUE for GTX
+            )
+
+
+        # TX clocking
+        # A PLL is used to generate the correct frequency for TXUSRCLK (UG476 Equation 3-1)
+        self.clock_domains.cd_cxp_gtx_tx = ClockDomain()
+        txpll_fb_clk = Signal()
+        txoutclk_buf = Signal()
+        txpll_clkout = Signal()
+
+        self.txpll_reset = Signal()
+        self.pll_daddr = Signal(7)
+        self.pll_dclk = Signal()
+        self.pll_den = Signal()
+        self.pll_din = Signal(16)
+        self.pll_dwen = Signal()
+
+        self.txpll_locked = Signal()
+        self.pll_dout = Signal(16)
+        self.pll_dready = Signal()
+        self.specials += [
+            Instance("PLLE2_ADV",
+                p_BANDWIDTH="HIGH",
+                o_LOCKED=self.txpll_locked,
+                i_RST=self.txpll_reset,
+                
+                p_CLKIN1_PERIOD=1e9/sys_clk_freq, # ns
+                i_CLKIN1=txoutclk_buf,
+
+                # VCO @ 1.25GHz 
+                p_CLKFBOUT_MULT=pll_fbout_mult, p_DIVCLK_DIVIDE=1,
+                i_CLKFBIN=txpll_fb_clk, o_CLKFBOUT=txpll_fb_clk, 
+
+                # frequency = linerate/40
+                p_CLKOUT0_DIVIDE=txusr_pll_div, p_CLKOUT0_PHASE=0.0, o_CLKOUT0=txpll_clkout,
+
+                # Dynamic Reconfiguration Ports
+                i_DADDR = self.pll_daddr,
+                i_DCLK = self.pll_dclk,
+                i_DEN = self.pll_den,
+                i_DI = self.pll_din,
+                i_DWE = self.pll_dwen,
+                o_DO = self.pll_dout,
+                o_DRDY = self.pll_dready,
+            ),
+            Instance("BUFG", i_I=self.txoutclk, o_O=txoutclk_buf),
+            Instance("BUFG", i_I=txpll_clkout, o_O=self.cd_cxp_gtx_tx.clk),
+            AsyncResetSynchronizer(self.cd_cxp_gtx_tx, ~self.txpll_locked & ~tx_init.done)
+        ]
+        self.comb += tx_init.restart.eq(self.tx_restart)
+
+        # RX clocking
+        # the CDR matches the required frequency for RXUSRCLK, no need for PLL 
+        # Slave Rx will use cxp_gtx_rx from master
+        if rx_mode == "single" or rx_mode == "master":
+            self.clock_domains.cd_cxp_gtx_rx = ClockDomain()
+            self.specials += [
+                Instance("BUFG", i_I=self.rxoutclk, o_O=self.cd_cxp_gtx_rx.clk),
+                AsyncResetSynchronizer(self.cd_cxp_gtx_rx, ~rx_init.done)
+            ]
+
+        self.comb += rx_init.restart.eq(self.rx_manual_restart)
+
+        # 8b10b Encoder/Decoder
+        self.comb += [
+            txdata.eq(Cat(self.encoder.output[0], self.encoder.output[1], self.encoder.output[2], self.encoder.output[3])),
+            self.decoders[0].input.eq(rxdata[:10]),
+            self.decoders[1].input.eq(rxdata[10:20]),
+            self.decoders[2].input.eq(rxdata[20:30]),
+            self.decoders[3].input.eq(rxdata[30:]),
+        ]
+
+        self.submodules.comma_aligner = comma_aligner = Comma_Aligner(0b0101111100)
+        self.comb += [
+            comma_aligner.data.eq(rxdata),
+            comma_aligner.comma_aligned.eq(comma_aligned),
+            comma_aligner.comma_realigned.eq(comma_realigned),
+            comma_aligner.comma_det.eq(comma_det),
+            comma_aligner_en.eq(comma_aligner.aligner_en),
+            self.rx_ready.eq(comma_aligner.ready_sys),
+        ]

src/gateware/cxp_frame_pipeline.py

@@ -0,0 +1,705 @@
+from migen import *
+from migen.genlib.coding import PriorityEncoder
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+from misoc.cores.liteeth_mini.mac.crc import LiteEthMACCRCEngine
+
+from cxp_pipeline import *
+# from src.gateware.cxp_pipeline import * # for sim only
+
+from types import SimpleNamespace
+from math import lcm
+
+pixel_width = 16
+pixel4x_layout = [
+    ("data", pixel_width*4),
+    ("valid", 4), 
+]
+
+def switch_endianness(s):
+    assert len(s) % 8 == 0
+    char = [s[i*8:(i+1)*8] for i in range(len(s)//8)]
+    return Cat(char[::-1])
+
+class EOP_Inserter(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                If(~((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                    self.sink.connect(self.source, omit={"ack", "eop"}),
+                ).Else(
+                    self.source.stb.eq(0),
+                )
+            ),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+            self.source.eop.eq(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1))),
+        ]
+
+class End_Of_Line_Inserter(Module):
+    def __init__(self):
+        self.l_size = Signal(3*char_width)
+
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint([("data", word_dw)]) # pixel data don't need k code
+        
+        # # #
+
+        # TODO: there maybe a reset bug where cxp_gtx_rx is not reset but frame size is changed
+        # cnt will be reset to last l_size instead of the new l_size resulting in wrong eop tag
+
+        # NOTE: because the self.sink.stb is only active after new_frame, the cnt is changed after the new_frame is high
+        # Also, after transmitting the last word, cnt = 1, so cnt will update to the correct self.l_size regardless 
+
+        cnt = Signal.like(self.l_size, reset=1)
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.sink.connect(self.source, omit={"ack", "eop", "k", "dchar", "dchar_k"}),
+                If(self.sink.stb,
+                    If(cnt == 1,
+                        cnt.eq(self.l_size)
+                    ).Else(
+                        cnt.eq(cnt - 1),
+                    )
+                ),
+            ),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+            # repurpose eop as end of line
+            self.source.eop.eq(cnt == 1),
+        ]
+
+class EOP_Marker(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        last_stb = Signal()
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.source.stb.eq(self.sink.stb),
+                self.source.payload.eq(self.sink.payload),
+            ),
+            last_stb.eq(self.sink.stb),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+            self.source.eop.eq(~self.sink.stb & last_stb),
+        ]
+
+class Stream_Arbiter(Module):
+    def __init__(self, n_downconn):
+        self.n_ext_active = Signal(max=n_downconn) 
+
+        self.sinks = [stream.Endpoint(word_layout_dchar) for _ in range(n_downconn)]
+        self.source = stream.Endpoint(word_layout_dchar)
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        read_mask = Signal.like(self.n_ext_active)
+        connect_case = dict((i, s.connect(self.source)) for i, s in enumerate(self.sinks))
+        fsm.act(
+            "COPY",
+            Case(read_mask, connect_case),
+            If(self.source.eop,
+                NextState("SWITCH_SOURCE"),
+            ),
+        )
+        
+        # Section 9.5.5 (CXP-001-2021)
+        # When Multiple connections are active, stream packets are transmitted in
+        # ascending order of Connection ID (which we currently only support ch1->2->3->4).
+        # And one connection shall be transmitting data at a time.
+        fsm.act(
+            "SWITCH_SOURCE",
+            If(read_mask == self.n_ext_active,
+                NextValue(read_mask, read_mask.reset),
+            ).Else(
+                NextValue(read_mask, read_mask + 1),
+            ),
+            NextState("COPY"),
+        )
+
+@ResetInserter()
+@CEInserter()
+class CXPCRC32(Module):
+    # Section 9.2.2.2 (CXP-001-2021)
+    width = 32
+    polynom = 0x04C11DB7
+    seed = 2**width - 1
+    check = 0x00000000
+
+    def __init__(self, data_width):
+        self.data = Signal(data_width)
+        self.value = Signal(self.width)
+        self.error = Signal()
+
+        # # #
+
+        self.submodules.engine = LiteEthMACCRCEngine(
+            data_width, self.width, self.polynom
+        )
+        reg = Signal(self.width, reset=self.seed)
+        self.sync += reg.eq(self.engine.next)
+        self.comb += [
+            self.engine.data.eq(self.data),
+            self.engine.last.eq(reg),
+            self.value.eq(reg[::-1]),
+            self.error.eq(reg != self.check),
+        ]
+
+# For verifying crc in stream data packet
+class CXPCRC32_Checker(Module):
+    def __init__(self):
+        self.error_cnt = Signal(16)
+
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+        self.submodules.crc = crc = CXPCRC32(word_dw)
+        self.comb += crc.data.eq(self.sink.data),
+
+        self.submodules.fsm = fsm = FSM(reset_state="INIT")
+        fsm.act("INIT",
+            crc.reset.eq(1),
+            NextState("CHECKING"),
+        )
+
+        fsm.act("RESET",
+            crc.reset.eq(1),
+            If(crc.error, NextValue(self.error_cnt, self.error_cnt + 1)),
+            NextState("CHECKING"),
+        )
+
+        fsm.act("CHECKING",
+            If(self.sink.stb & self.sink.eop,
+                # discard the crc
+                self.sink.ack.eq(1),
+                NextState("RESET"),
+            ).Else(
+                self.sink.connect(self.source),
+            ),
+            If(self.sink.stb,
+                crc.ce.eq(1),
+            ),
+        )
+    
+        
+class Stream_Broadcaster(Module):
+    def __init__(self, n_buffer, default_id=0):
+        assert n_buffer > 0
+
+        self.routing_table = [Signal(char_width) for _ in range(1, n_buffer)]
+
+        self.sources = [stream.Endpoint(word_layout_dchar) for _ in range(n_buffer)]
+        self.sink = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+
+        
+
+        self.stream_id = Signal(char_width)
+        self.pak_tag = Signal(char_width)
+        self.stream_pak_size = Signal(char_width * 2)
+
+        self.submodules.fsm = fsm = FSM(reset_state="WAIT_HEADER")
+
+        fsm.act(
+            "WAIT_HEADER",
+            NextValue(self.stream_id, self.stream_id.reset),
+            NextValue(self.pak_tag, self.pak_tag.reset),
+            NextValue(self.stream_pak_size, self.stream_pak_size.reset),
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_id, self.sink.dchar),
+                NextState("GET_PAK_TAG"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_TAG",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.pak_tag, self.sink.dchar),
+                NextState("GET_PAK_SIZE_0"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_SIZE_0",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_pak_size[8:], self.sink.dchar),
+                NextState("GET_PAK_SIZE_1"),
+            ),
+        )
+
+        fsm.act(
+            "GET_PAK_SIZE_1",
+            self.sink.ack.eq(1),
+            If(
+                self.sink.stb,
+                NextValue(self.stream_pak_size[:8], self.sink.dchar),
+                NextState("STORE_BUFFER"),
+            ),
+        )
+
+        # routing decoder
+        sel = Signal(n_buffer)
+        no_match = Signal()
+        self.comb += sel[0].eq(self.stream_id == default_id)
+        for i, routing_id in enumerate(self.routing_table):
+            self.comb += sel[i+1].eq(self.stream_id == routing_id)
+        # DEBUG: disrecard the stream id = 0 rule
+        # self.comb += source_sel[0].eq(self.stream_id == self.routing_table[0])
+
+        # ensure the lower source has priority when two or more bits of sel are high
+        self.submodules.coder = coder = PriorityEncoder(n_buffer)
+        sel_r = Signal.like(coder.o)
+        self.sync += [
+            coder.i.eq(sel),
+            sel_r.eq(coder.o),
+            no_match.eq(coder.n),
+        ]
+
+        routing = dict((i, self.sink.connect(s))for i, s in enumerate(self.sources))
+        routing["default"] = self.sink.ack.eq(1) # discard if invalid
+        fsm.act(
+            "STORE_BUFFER",
+            If(no_match,
+                self.sink.ack.eq(1),
+            ).Else(
+                Case(sel_r, routing),
+            ),
+            # assume downstream is not blocked
+            If(self.sink.stb,
+                NextValue(self.stream_pak_size, self.stream_pak_size - 1),
+                If(self.stream_pak_size == 0,
+                    NextState("WAIT_HEADER"),
+                )
+            ),
+        )
+
+class Frame_Header_Decoder(Module):
+    def __init__(self):
+        self.format_error = Signal()
+        self.decode_err = Signal()
+
+        self.new_frame = Signal()
+        self.new_line = Signal()
+
+        # Table 47 (CXP-001-2021)
+        n_metadata_chars = 23
+        img_header_layout = [
+            ("stream_id", char_width),
+            ("source_tag", 2*char_width), 
+            ("x_size", 3*char_width), 
+            ("x_offset", 3*char_width), 
+            ("y_size", 3*char_width), 
+            ("y_offset", 3*char_width), 
+            ("l_size", 3*char_width), # number of data words per image line 
+            ("pixel_format", 2*char_width), 
+            ("tap_geo", 2*char_width), 
+            ("flag", char_width), 
+        ]
+        assert layout_len(img_header_layout) == n_metadata_chars*char_width  
+
+
+        # # #
+
+        # TODO: decode Image header, line break
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
+                NextState("DECODE"),
+            )
+        )
+
+        fsm.act("COPY",
+            # until for new line or new frame
+            If((self.sink.stb & (self.sink.dchar == KCode["stream_marker"]) & (self.sink.dchar_k == 1)),
+                self.sink.ack.eq(1),
+                NextState("DECODE"),
+            ).Else(
+                self.sink.connect(self.source),
+            )
+        )
+
+        type = {
+            "new_frame": 0x01,
+            "line_break": 0x02,
+        }
+
+        cnt = Signal(max=n_metadata_chars)
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(self.sink.dchar, {
+                    type["new_frame"]: [
+                        self.new_frame.eq(1),
+                        NextValue(cnt, cnt.reset),
+                        NextState("GET_FRAME_DATA"),
+                    ],
+                    type["line_break"]: [
+                        self.new_line.eq(1),
+                        NextState("COPY"),
+                    ],
+                    "default": [
+                         self.decode_err.eq(1),
+                         # discard all data until valid frame header
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+
+        packet_buffer = Signal(layout_len(img_header_layout))
+        case = dict(
+            (i, NextValue(packet_buffer[8*i:8*(i+1)], self.sink.dchar))
+            for i in range(n_metadata_chars)
+        )
+        fsm.act("GET_FRAME_DATA",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(cnt, case),
+                If(cnt == n_metadata_chars - 1,
+                    NextState("COPY"),
+                    NextValue(cnt, cnt.reset),
+                ).Else(
+                    NextValue(cnt, cnt + 1),
+                ),
+            ),
+        )
+
+        # dissect packet 
+        self.metadata = SimpleNamespace()
+        idx = 0
+        for name, size in img_header_layout:
+            # CXP use MSB even when sending duplicate chars
+            setattr(self.metadata, name, switch_endianness(packet_buffer[idx:idx+size]))
+            idx += size
+
+class Custom_Pixel_Gearbox(Module):
+    def __init__(self, size):
+        assert size in [8]
+
+        self.x_size = Signal(3*char_width)
+
+        i_dw, o_dw = word_dw, size*4
+        self.sink = stream.Endpoint([("data", i_dw)])
+        self.source = stream.Endpoint(pixel4x_layout)
+
+        # # #
+
+        io_lcm = lcm(i_dw, o_dw)
+        if (io_lcm//i_dw) < 2:
+            io_lcm = io_lcm * 2
+        if (io_lcm//o_dw) < 2:
+            io_lcm = io_lcm * 2
+
+
+        self.shift_register = Signal(io_lcm, reset_less=True)
+
+        # Input sink
+
+        i_inc   = Signal()
+        i_count = Signal(max=io_lcm//i_dw)
+
+        self.comb += [
+            self.sink.ack.eq(1), # assume downstream is not blocked
+            i_inc.eq(self.sink.stb),
+        ]
+        
+        self.sync += [
+            If(i_inc, 
+                If(i_count == ((io_lcm//i_dw) - 1),
+                    i_count.eq(i_count.reset),
+                ).Else(
+                    i_count.eq(i_count + 1),
+                )
+            ),
+        ]
+        
+        i_cases = {}
+        for i in range(io_lcm//i_dw):
+            i_cases[i] = [
+                self.shift_register[i_dw*i:i_dw*(i+1)].eq(self.sink.data),
+            ]
+        self.sync += If(self.sink.stb, Case(i_count, i_cases))
+
+        # Output source
+
+        level   = Signal(max=io_lcm)
+        o_inc   = Signal()
+        o_count = Signal(max=io_lcm//o_dw)
+
+        self.comb += [
+            self.source.stb.eq(level >= o_dw),
+            o_inc.eq(self.source.stb & self.source.ack)
+        ]
+
+        self.sync += [
+            If(o_inc, 
+                If(o_count == ((io_lcm//o_dw) - 1),
+                    o_count.eq(o_count.reset),
+                ).Else(
+                    o_count.eq(o_count + 1),
+                )
+            ),
+            If(i_inc & ~o_inc, level.eq(level + i_dw)),
+            If(~i_inc & o_inc, level.eq(level - o_dw)),
+            If(i_inc & o_inc, level.eq(level + i_dw - o_dw)),
+        ]
+
+        o_cases = {}
+        for i in range(io_lcm//o_dw):
+            o_cases[i] = []
+            for j in range(4):
+                o_cases[i].append(
+                    self.source.data[pixel_width * j : pixel_width * (j + 1)].eq(
+                        self.shift_register[(o_dw * i) + (size * j) : (o_dw * i) + (size * (j + 1))]
+                    )
+                )
+        self.comb += Case(o_count, o_cases)
+
+        # Handle line break
+
+        # precalcule which pixels are valid
+        self.valid = Signal(4)
+        bit_cases = {
+            0: self.valid.eq(0b1111),
+            1: self.valid.eq(0b0001),
+            2: self.valid.eq(0b0011),
+            3: self.valid.eq(0b0111),
+        }
+        self.sync += Case(self.x_size[:2], bit_cases)
+
+        # TODO: reset the o_count & i_count after eop
+        line_break_r = Signal()
+        self.sync += [
+            line_break_r.eq(self.sink.eop),
+            If(line_break_r,
+            )
+        ]
+
+        # get which last pixels are valid
+        # use end of line to reset o_count, i_count, level & stb the last pixel 
+        self.comb += [
+            If(line_break_r,
+                self.source.valid.eq(self.valid),
+            ).Else(
+                self.source.valid.eq(0b1111),
+            )
+        ]
+
+
+        
+
+
+class Frame_Deserializer(Module):
+    def __init__(self, width, pixel_size):
+        self.new_frame = Signal()
+        self.l_size = Signal(3*char_width)
+        self.x_size = Signal(3*char_width)
+
+        # # #
+
+        self.submodules.eol_inserter = eol_inserter = End_Of_Line_Inserter()
+        self.sync += eol_inserter.l_size.eq(self.l_size),
+
+
+        self.submodules.gearbox = gearbox = Custom_Pixel_Gearbox(8)
+        self.sync += gearbox.x_size.eq(self.x_size),
+
+        self.comb += eol_inserter.source.connect(gearbox.sink)
+        
+        self.sink = eol_inserter.sink
+        self.source = gearbox.source
+
+        
+
+
+        # # TODO: use this to control mux
+        # Table 34 (CXP-001-2021)
+        pix_fmt = {
+            "mono8": 0x0101,
+            "mono10": 0x0102,
+            "mono12": 0x0103,
+            "mono14": 0x0104,
+            "mono16": 0x0105,
+        }
+        # self.sync += [ 
+        #     pixel_format_r.eq(header_decoder.metadata.pixel_format),
+        #     Case(pixel_format_r, 
+        #         {
+        #             pix_fmt["mono8"]: pix_size.eq(8),
+        #             pix_fmt["mono10"]: pix_size.eq(10),
+        #             pix_fmt["mono12"]: pix_size.eq(12),
+        #             pix_fmt["mono14"]: pix_size.eq(14),
+        #             pix_fmt["mono16"]: pix_size.eq(16),
+        #             "default": pix_size.eq(pix_size.reset),
+        #         }
+        #     )
+        # ]
+
+
+def inc_mod(s, m):
+    return [s.eq(s + 1), If(s == (m -1), s.eq(0))]
+
+
+class Pixel_Gearbox(Module):
+    def __init__(self, i_dw, o_dw):
+        self.sink   = sink   = stream.Endpoint([("data", i_dw)])
+        self.source = source = stream.Endpoint([("data", o_dw)])
+
+        # # #
+
+        # From Litex
+
+        # TODO: change this to purpose built module
+        # TODO: handle linebreak stb
+        # TODO: handle the last line may only contain 1, 2, 3 or 4 pixels
+
+        # Section 10.4.2 (CXP-001-2021)
+        # the line data need to be fitted inside of 32*nbits where n is integers
+        # extra bits are padded with zero
+        # -> perhaps use this as advantage?? it's provided as DsizeL
+        # -> use DsizeL as another counter to indicate line break?
+
+        io_lcm = lcm(i_dw, o_dw)
+        if (io_lcm//i_dw) < 2:
+            io_lcm = io_lcm * 2
+        if (io_lcm//o_dw) < 2:
+            io_lcm = io_lcm * 2
+
+        # Control path
+
+        level   = Signal(max=io_lcm)
+        i_inc   = Signal()
+        i_count = Signal(max=io_lcm//i_dw)
+        o_inc   = Signal()
+        o_count = Signal(max=io_lcm//o_dw)
+
+        self.comb += [
+            sink.ack.eq(1),
+            # sink.ack.eq(level < (io_lcm - i_dw)),
+            source.stb.eq(level >= o_dw),
+        ]
+        self.comb += [
+            i_inc.eq(sink.stb & sink.ack),
+            o_inc.eq(source.stb & source.ack)
+        ]
+        self.sync += [
+            If(i_inc, *inc_mod(i_count, io_lcm//i_dw)),
+            If(o_inc, *inc_mod(o_count, io_lcm//o_dw)),
+            If(i_inc & ~o_inc, level.eq(level + i_dw)),
+            If(~i_inc & o_inc, level.eq(level - o_dw)),
+            If(i_inc & o_inc, level.eq(level + i_dw - o_dw)),
+        ]
+
+        # Data path
+
+        shift_register = Signal(io_lcm, reset_less=True)
+
+        i_cases = {}
+        i_data  = Signal(i_dw)
+
+        self.comb += i_data.eq(sink.data)
+        for i in range(io_lcm//i_dw):
+            i_cases[i] = shift_register[io_lcm - i_dw*(i+1):io_lcm - i_dw*i].eq(i_data)
+        self.sync += If(sink.stb & sink.ack, Case(i_count, i_cases))
+
+        o_cases = {}
+        o_data  = Signal(o_dw)
+        for i in range(io_lcm//o_dw):
+            o_cases[i] = o_data.eq(shift_register[io_lcm - o_dw*(i+1):io_lcm - o_dw*i])
+        self.comb += Case(o_count, o_cases)
+        self.comb += source.data.eq(o_data)
+
+
+
+class ROI_Pipeline(Module):
+    def __init__(self, res_width=32, pixel_size=16):
+
+        # NOTE: csr need to stay outside since this module need to be cdr in the CXP_FRAME_Pipeline module
+        # NOTE: TapGeo other than 1X-1Y are not supported
+        # TODO: match pixel and see whether the it matches the supported ones (via csr perhaps?)
+
+        self.submodules.crc_checker = crc_checker = CXPCRC32_Checker()
+        self.submodules.header_decoder = header_decoder = Frame_Header_Decoder()
+        self.submodules.deserializer = deserializer = Frame_Deserializer(res_width, pixel_size)
+
+        self.comb += [
+            deserializer.new_frame.eq(header_decoder.new_frame),
+            deserializer.l_size.eq(header_decoder.metadata.l_size),
+            deserializer.x_size.eq(header_decoder.metadata.x_size),
+        ]
+
+        self.pipeline = [crc_checker, header_decoder, deserializer]
+        for s, d in zip(self.pipeline, self.pipeline[1:]):
+            self.comb += s.source.connect(d.sink)
+        self.sink = self.pipeline[0].sink
+
+        # DEBUG
+        self.source = self.pipeline[-1].source
+        self.comb += self.source.ack.eq(1) # simulated a proper consumer, idk why but without this it will destory timing
+
+class Frame_Packet_Router(Module):
+    # packet size expressed in bits
+    def __init__(self, downconns, framebuffer, packet_size, pmod_pads):
+        n_downconn = len(downconns)
+        n_buffer = len(framebuffer)
+        assert n_downconn > 0 and n_buffer > 0
+
+        self.n_ext_active = Signal(max=n_downconn)
+        self.routing_table = [Signal(char_width) for _ in range(1, n_buffer)]
+
+        # # #
+        
+        #                  +----------+     +-------------+
+        # eop marker ----->|          |     |             |------> crc checker 
+        #                  | arbiter  |---->| broadcaster |
+        # eop marker ----->| need eop |     |             |------> crc checker 
+        #                  +----------+     +-------------+
+        #
+
+        self.submodules.arbiter = arbiter = Stream_Arbiter(n_downconn)
+        self.sync += arbiter.n_ext_active.eq(self.n_ext_active)
+
+        self.submodules.broadcaster = broadcaster = Stream_Broadcaster(n_buffer)
+        for i, s in enumerate(self.routing_table):
+            self.sync += broadcaster.routing_table[i].eq(s)
+
+        for i, d in enumerate(downconns):
+            # eop is needed for arbiter and crc checker to work correctly
+            eop_marker = EOP_Inserter()
+            self.submodules += eop_marker
+            self.comb += [
+                d.source.connect(eop_marker.sink),
+                eop_marker.source.connect(arbiter.sinks[i])
+            ]
+
+        self.comb += arbiter.source.connect(broadcaster.sink)
+
+        for i, fb in enumerate(framebuffer):
+            self.comb += broadcaster.sources[i].connect(fb.sink),

src/gateware/cxp_pipeline.py

@@ -0,0 +1,613 @@
+from migen import *
+from migen.genlib.cdc import MultiReg 
+from misoc.interconnect.csr import *
+from misoc.interconnect import stream
+
+from functools import reduce
+from itertools import combinations
+from operator import or_, and_
+
+char_width = 8
+char_layout = [("data", char_width), ("k", char_width//8)]
+
+word_dw = 32
+word_layout = [("data", word_dw), ("k", word_dw//8)]
+
+word_layout_dchar = [
+    ("data", word_dw),
+    ("k", word_dw//8), 
+    ("dchar", char_width), 
+    ("dchar_k", char_width//8),
+]
+
+buffer_count = 4
+buffer_depth = 512
+
+def K(x, y):
+    return ((y << 5) | x)
+
+KCode = {
+    "pak_start" : C(K(27, 7), char_width),
+    "io_ack" : C(K(28, 6), char_width), 
+    "trig_indic_28_2" : C(K(28, 2), char_width),
+    "stream_marker" : C(K(28, 3), char_width),
+    "trig_indic_28_4" : C(K(28, 4), char_width),
+    "pak_end" : C(K(29, 7), char_width),
+    "idle_comma" : C(K(28, 5), char_width),
+    "idle_alignment" : C(K(28, 1), char_width),
+}
+
+class Packet_Wrapper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                NextState("INSERT_HEADER"),
+            )
+        )
+
+        fsm.act("INSERT_HEADER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_start"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            self.source.eop.eq(0),
+            If(self.sink.stb & self.sink.eop & self.source.ack,
+                NextState("INSERT_FOOTER"),
+            ),
+        )
+
+        fsm.act("INSERT_FOOTER",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["pak_end"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            self.source.eop.eq(1),
+            If(self.source.ack, NextState("IDLE")),
+        )
+        
+class TX_Trigger(Module):
+    def __init__(self):
+        self.stb = Signal()
+        self.delay = Signal(char_width) 
+        self.linktrig_mode = Signal()
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+        self.source = stream.Endpoint(char_layout)
+
+        # Table 15 & 16 (CXP-001-2021)
+        # Send [K28.2, K28.4, K28.4] or [K28.4, K28.2, K28.2] and 3x delay as trigger packet 
+
+        trig_packet = [Signal(char_width), Signal(char_width), Signal(char_width), self.delay, self.delay, self.delay]
+        trig_packet_k = [1, 1, 1, 0, 0, 0]
+        self.comb += [
+            If(self.linktrig_mode,
+                trig_packet[0].eq(KCode["trig_indic_28_4"]),
+                trig_packet[1].eq(KCode["trig_indic_28_2"]),
+                trig_packet[2].eq(KCode["trig_indic_28_2"]),
+            ).Else(
+                trig_packet[0].eq(KCode["trig_indic_28_2"]),
+                trig_packet[1].eq(KCode["trig_indic_28_4"]),
+                trig_packet[2].eq(KCode["trig_indic_28_4"]),
+            ),
+        ]
+        
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        cnt = Signal(max=6)
+        fsm.act("COPY",
+            NextValue(cnt, cnt.reset),
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_TRIG"))
+        )
+
+        fsm.act("WRITE_TRIG",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Array(trig_packet)[cnt]),
+            self.source.k.eq(Array(trig_packet_k)[cnt]),
+            If(self.source.ack,
+                If(cnt == 5,
+                    NextState("COPY"),
+                ).Else(
+                    NextValue(cnt, cnt + 1),
+                )
+            )
+        )
+
+class Idle_Word_Inserter(Module):
+    def __init__(self):
+        # Section 9.2.5 (CXP-001-2021)
+        # Send K28.5, K28.1, K28.1, D21.5  as idle word
+        self.submodules.fsm = fsm = FSM(reset_state="WRITE_IDLE")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+
+        # Section 9.2.5.1 (CXP-001-2021)
+        # IDLE should be transmitter every 10000 words
+        cnt = Signal(max=10000, reset=9999)
+        
+        fsm.act("WRITE_IDLE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Cat(KCode["idle_comma"], KCode["idle_alignment"], KCode["idle_alignment"], C(0xB5, char_width))),
+            self.source.k.eq(Cat(1, 1, 1, 0)),
+
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                self.sink.ack.eq(0),
+                If(self.source.ack,
+                    NextValue(cnt, cnt.reset),
+                    NextState("COPY"),
+                )
+            ),
+        )
+
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            # increment when upstream has data and got ack
+            If(self.sink.stb & self.source.ack, NextValue(cnt, cnt - 1)),
+            If((( (~self.sink.stb) | (self.sink.eop) | (cnt == 0) ) & self.source.ack), NextState("WRITE_IDLE"))
+        )
+
+
+class Trigger_ACK_Inserter(Module):
+    def __init__(self):
+        self.stb = Signal()
+
+        # # #
+
+        # Section 9.3.2 (CXP-001-2021)
+        # Send 4x K28.6 and 4x 0x01 as trigger packet ack
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+        
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout)
+        fsm.act("COPY",
+            self.sink.connect(self.source),
+            If(self.stb, NextState("WRITE_ACK0"))
+        )
+
+        fsm.act("WRITE_ACK0",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(KCode["io_ack"], 4)),
+            self.source.k.eq(Replicate(1, 4)),
+            If(self.source.ack, NextState("WRITE_ACK1")),
+        )
+
+        fsm.act("WRITE_ACK1",
+            self.sink.ack.eq(0),
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x01, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack, NextState("COPY")),
+        )
+
+
+@FullMemoryWE()
+class TX_Bootstrap(Module, AutoCSR):
+    def __init__(self):
+        self.tx_word_len = CSRStorage(log2_int(buffer_depth))
+        self.tx = CSR()
+        self.tx_testseq = CSR()
+
+        self.tx_busy = CSRStatus()
+
+        # # #
+        
+        self.specials.mem = mem = Memory(word_dw, buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port()
+        self.source = stream.Endpoint(word_layout)
+
+        # increment addr in the same cycle the moment addr_inc is high
+        # as memory takes one cycle to shift to the correct addr
+        addr_next = Signal(log2_int(buffer_depth))
+        addr = Signal.like(addr_next)
+        addr_rst = Signal()
+        addr_inc = Signal()
+        self.sync += addr.eq(addr_next),
+
+        self.comb += [
+            addr_next.eq(addr),
+            If(addr_rst,
+                addr_next.eq(addr_next.reset),
+            ).Elif(addr_inc,
+                addr_next.eq(addr + 1),
+            ),
+            mem_port.adr.eq(addr_next),
+        ]
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+        self.sync += self.tx_busy.status.eq(~fsm.ongoing("IDLE"))
+
+        cnt = Signal(max=0xFFF)
+        fsm.act("IDLE",
+            addr_rst.eq(1),
+            If(self.tx.re, NextState("TRANSMIT")),
+            If(self.tx_testseq.re, 
+                NextValue(cnt, cnt.reset),
+                NextState("WRITE_TEST_PACKET_TYPE"),
+            )
+        )
+
+        fsm.act("TRANSMIT",
+            self.source.stb.eq(1),
+            self.source.data.eq(mem_port.dat_r),
+            If(self.source.ack,
+                addr_inc.eq(1),
+            ),
+            If(addr_next == self.tx_word_len.storage,
+                self.source.eop.eq(1),
+                NextState("IDLE")
+            )
+        )
+
+        fsm.act("WRITE_TEST_PACKET_TYPE",
+            self.source.stb.eq(1),
+            self.source.data.eq(Replicate(C(0x04, char_width), 4)),
+            self.source.k.eq(Replicate(0, 4)),
+            If(self.source.ack,NextState("WRITE_TEST_COUNTER"))
+        )
+
+        fsm.act("WRITE_TEST_COUNTER",
+            self.source.stb.eq(1),
+            self.source.data[:8].eq(cnt[:8]),
+            self.source.data[8:16].eq(cnt[:8]+1),
+            self.source.data[16:24].eq(cnt[:8]+2),
+            self.source.data[24:].eq(cnt[:8]+3),
+            self.source.k.eq(Cat(0, 0, 0, 0)),
+            If(self.source.ack,
+                If(cnt == 0xFFC,
+                    self.source.eop.eq(1),
+                    NextState("IDLE")
+                ).Else(
+                    NextValue(cnt, cnt + 4),
+                )
+               
+            )
+        )
+
+class RX_Debug_Buffer(Module,AutoCSR):
+    def __init__(self, layout, size):
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, size, True)
+        self.sink = buf_out.sink
+
+        self.inc = CSR()
+        self.dout_valid = CSRStatus()
+
+        self.dout_pak = CSRStatus(word_dw)
+        self.kout_pak = CSRStatus(word_dw//8)
+        self.crc_error = CSRStatus()
+        self.eop = CSRStatus()
+
+        self.sync += [
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_valid.status.eq(buf_out.source.stb),
+            # output
+            self.eop.status.eq(buf_out.source.eop),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            # self.crc_error.status.eq(buf_out.source.error)
+        ]
+
+class Duplicated_Char_Decoder(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        # # #
+
+
+        # For duplicated characters, an error correction method (e.g. majority voting) is required to meet the CXP spec:
+        # RX decoder should immune to single bit errors when handling duplicated characters - Section 9.2.2.1 (CXP-001-2021)
+        # 
+        #
+        #                                 32
+        #             +--->  buffer  -----/-----+
+        #         32  |                         |            32+8(dchar)
+        # sink ---/---+                         ---> source -----/-----> downstream
+        #             |                8(dchar) |                        decoders
+        #             +---> majority -----/-----+
+        #                   voting
+        # 
+        #
+        # Due to the tight setup/hold time requiremnt for 12.5Gbps CXP, the voting logic cannot be implemented as combinational logic
+        # Hence, a pipeline approach is needed to avoid any s/h violation, where the majority voting result are pre-calculate and injected into the bus immediate after the PHY.
+        # And any downstream modules can access the voting result anytime
+
+        # cycle 1 - buffer data & calculate intermediate result  
+        buffer = stream.Endpoint(word_layout)
+        self.sync += [
+            If((~buffer.stb | buffer.ack),
+                self.sink.connect(buffer, omit={"ack"}),
+            )
+        ]
+        self.comb += self.sink.ack.eq(~buffer.stb | buffer.ack)
+        
+        # calculate ABC, ABD, ACD, BCD  
+        char = [[self.sink.data[i*8:(i+1)*8], self.sink.k[i]] for i in range(4)]
+        voters = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
+
+        for i, comb in enumerate(combinations(char, 3)):
+            self.sync += [
+                If((~buffer.stb | buffer.ack),
+                    voters[i].data.eq(reduce(and_, [code[0] for code in comb])),
+                    voters[i].k.eq(reduce(and_, [code[1] for code in comb])),
+                )
+            ]
+
+
+        # cycle 2 - inject the voting result 
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                buffer.connect(self.source, omit={"ack", "dchar", "dchar_k"}),
+                self.source.dchar.eq(Replicate(reduce(or_, [v.data for v in voters]), 4)),
+                self.source.dchar_k.eq(Replicate(reduce(or_, [v.k for v in voters]), 4)),
+            )
+        ]
+        self.comb += buffer.ack.eq(~self.source.stb | self.source.ack)
+
+
+@FullMemoryWE()
+class RX_Bootstrap(Module):
+    def __init__(self):
+        self.packet_type = Signal(8)
+
+        self.decode_err = Signal()
+        self.buffer_err = Signal()
+
+        self.test_err_cnt = Signal(16)
+        self.test_pak_cnt = Signal(16)
+        self.test_cnt_reset = Signal()
+        # # #
+
+        type = {
+            "data_stream": 0x01,
+            "control_ack_no_tag": 0x03,
+            "test_packet": 0x04,
+            "control_ack_with_tag": 0x06,
+            "event": 0x07,
+            "heartbeat": 0x09,
+        }
+
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.submodules.fsm = fsm = FSM(reset_state="IDLE")
+
+        fsm.act("IDLE",
+            self.sink.ack.eq(1),
+            If((self.sink.stb & (self.sink.dchar == KCode["pak_start"]) & (self.sink.dchar_k == 1)),
+                NextState("DECODE"),
+            )
+        )
+
+        cnt = Signal(max=0x100)
+        addr_nbits = log2_int(buffer_depth)
+        addr = Signal(addr_nbits)
+        test_pak = Signal()
+        fsm.act("DECODE",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                Case(self.sink.dchar, {
+                    type["data_stream"]: NextState("STREAMING"),
+                    type["test_packet"]: [
+                        test_pak.eq(1),
+                        NextValue(cnt, cnt.reset),
+                        NextState("VERIFY_TEST_PATTERN"),
+                    ],
+                    type["control_ack_no_tag"]:[
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["control_ack_with_tag"]:[
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["event"]: [
+                        NextValue(self.packet_type, self.sink.dchar),
+                        NextValue(addr, addr.reset),
+                        NextState("LOAD_BUFFER"),
+                    ],
+                    type["heartbeat"] : [
+                         # TODO: handle heartbeat
+                         NextState("IDLE"),
+                    ],
+                    "default": [
+                         self.decode_err.eq(1),
+                         # wait till next valid packet
+                         NextState("IDLE"),
+                    ],
+                }),
+            )
+        )
+        # For stream data packet
+        fsm.act("STREAMING",
+            self.sink.connect(self.source),
+            # assume downstream is not blocked
+            If((self.sink.stb & (self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                NextState("IDLE")
+            )      
+        )
+
+        # Section 9.9.1 (CXP-001-2021)
+        # the received test data packet (0x00, 0x01 ... 0xFF) 
+        # need to be compared against the local test sequence generator
+        # TODO: improve this to avoid tight setup/hold time
+        test_err = Signal()
+        fsm.act("VERIFY_TEST_PATTERN",
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                    NextState("IDLE"),
+                ).Else(
+                    If(self.sink.data[:8] != cnt, 
+                        test_err.eq(1),
+                    ).Elif(self.sink.data[8:16] != cnt + 1,
+                        test_err.eq(1),
+                    ).Elif(self.sink.data[16:24] != cnt + 2,
+                        test_err.eq(1),
+                    ).Elif(self.sink.data[24:] != cnt + 3,
+                        test_err.eq(1),
+                    ),
+                    
+                    If(cnt == 0xFC,
+                        NextValue(cnt, cnt.reset),
+                    ).Else(
+                        NextValue(cnt, cnt + 4)
+                    )
+                )
+            )
+                
+        )
+
+        self.sync += [
+            If(self.test_cnt_reset,
+                self.test_err_cnt.eq(self.test_err_cnt.reset),
+            ).Elif(test_err,
+                self.test_err_cnt.eq(self.test_err_cnt + 1),
+            ),
+            If(self.test_cnt_reset,
+                self.test_pak_cnt.eq(self.test_pak_cnt.reset),
+            ).Elif(test_pak,
+                self.test_pak_cnt.eq(self.test_pak_cnt + 1),
+            )
+        ]
+
+        # A circular buffer for firmware to read packet from
+        self.specials.mem = mem = Memory(word_dw, buffer_count*buffer_depth)
+        self.specials.mem_port = mem_port = mem.get_port(write_capable=True)
+
+        # buffered mem_port to improve timing
+        buf_mem_we = Signal.like(mem_port.we)
+        buf_mem_dat_w = Signal.like(mem_port.dat_w)
+        buf_mem_adr = Signal.like(mem_port.adr)
+        self.sync += [
+            mem_port.we.eq(buf_mem_we),
+            mem_port.dat_w.eq(buf_mem_dat_w),
+            mem_port.adr.eq(buf_mem_adr)
+        ]
+
+        write_ptr = Signal(log2_int(buffer_count))
+        self.write_ptr_sys = Signal.like(write_ptr)
+        self.specials += MultiReg(write_ptr, self.write_ptr_sys),
+
+        self.comb += [
+            buf_mem_adr[:addr_nbits].eq(addr),
+            buf_mem_adr[addr_nbits:].eq(write_ptr),
+        ]
+
+        # For control ack, event packet
+        fsm.act("LOAD_BUFFER",
+            buf_mem_we.eq(0),
+            self.sink.ack.eq(1),
+            If(self.sink.stb,
+                If(((self.sink.dchar == KCode["pak_end"]) & (self.sink.dchar_k == 1)),
+                    NextState("MOVE_BUFFER_PTR"),
+                ).Else(
+                    buf_mem_we.eq(1),
+                    buf_mem_dat_w.eq(self.sink.data),
+                    NextValue(addr, addr + 1),
+                    If(addr == buffer_depth - 1,
+                        # discard the packet
+                        self.buffer_err.eq(1),
+                        NextState("IDLE"),
+                    )
+                )
+            )
+        )
+
+        self.read_ptr_rx = Signal.like(write_ptr)
+        fsm.act("MOVE_BUFFER_PTR",
+            self.sink.ack.eq(0),
+            If(write_ptr + 1 == self.read_ptr_rx,
+                # if next one hasn't been read, overwrite the current buffer when new packet comes in
+                self.buffer_err.eq(1),
+            ).Else(
+                NextValue(write_ptr, write_ptr + 1),
+            ),
+            NextState("IDLE"),
+        )
+
+class Trigger_Ack_Checker(Module, AutoCSR):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout_dchar)
+
+        self.ack = Signal()
+
+        # # #
+
+        self.submodules.fsm = fsm = FSM(reset_state="COPY")
+
+        fsm.act("COPY",
+            If((self.sink.stb & (self.sink.dchar == KCode["io_ack"]) & (self.sink.dchar_k == 1)),
+                # discard K28,6
+                self.sink.ack.eq(1),
+                NextState("CHECK_ACK")
+            ).Else(
+                self.sink.connect(self.source),
+            )
+        )
+
+        fsm.act("CHECK_ACK",
+            If(self.sink.stb,
+                NextState("COPY"),
+                # discard the word after K28,6
+                self.sink.ack.eq(1),
+                If((self.sink.dchar == 0x01) & (self.sink.dchar_k == 0),
+                    self.ack.eq(1),
+                )
+            )
+        )
+
+class Buffer(Module):
+    def __init__(self, layout, omits=None):
+        self.sink = stream.Endpoint(layout)
+        self.source = stream.Endpoint(layout)
+
+        # # #
+
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.sink.connect(self.source, omit={"ack"}.union(omits) if omits else {"ack"}),
+            ),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+        ]
+
+class DChar_Dropper(Module):
+    def __init__(self):
+        self.sink = stream.Endpoint(word_layout_dchar)
+        self.source = stream.Endpoint(word_layout)
+
+        # # #
+
+        self.sync += [
+            If((~self.source.stb | self.source.ack),
+                self.sink.connect(self.source, omit={"ack", "dchar", "dchar_k", "error"}),
+            ),
+        ]
+        self.comb += [
+            self.sink.ack.eq(~self.source.stb | self.source.ack),
+        ]
+

src/gateware/cxp_rtio.py

@@ -0,0 +1,12 @@
+# Clocking/Reset
+# Create rio and rio_phy domains based on sys
+# with reset controlled by CSR.
+#
+# The `rio` CD contains logic that is reset with `core.reset()`.
+# That's state that could unduly affect subsequent experiments,
+# i.e. input overflows caused by input gates left open, FIFO events far
+# in the future blocking the experiment, pending RTIO or
+# wishbone bus transactions, etc.
+# The `rio_phy` CD contains state that is maintained across
+# `core.reset()`, i.e. TTL output state, OE, DDS state.
+

src/gateware/cxp_upconn.py

@@ -0,0 +1,196 @@
+from math import ceil
+
+from migen import *
+
+from misoc.cores.code_8b10b import SingleEncoder
+from misoc.interconnect import stream
+from misoc.interconnect.csr import *
+
+from cxp_pipeline import char_layout
+
+@ResetInserter()
+class UpConn_ClockGen(Module):
+    def __init__(self, sys_clk_freq):
+        self.clk = Signal()
+        self.clk_10x = Signal() # 20.83MHz 48ns or 41.66MHz 24ns
+
+        self.freq2x_enable = Signal()
+        # # #
+
+        period = 1e9/sys_clk_freq
+        max_count = ceil(48/period)
+        counter = Signal(max=max_count, reset=max_count-1)
+
+        clk_div = Signal(max=10, reset=9)
+
+        self.sync += [
+            self.clk.eq(0),
+            self.clk_10x.eq(0),
+
+            If(counter == 0,
+                self.clk_10x.eq(1),
+                If(self.freq2x_enable,
+                    counter.eq(int(max_count/2)-1),
+                ).Else(
+                    counter.eq(counter.reset),
+                ),
+            ).Else(
+                counter.eq(counter-1),
+            ),
+
+            If(counter == 0,
+                If(clk_div == 0,
+                    self.clk.eq(1),
+                    clk_div.eq(clk_div.reset),
+                ).Else(
+                    clk_div.eq(clk_div-1),
+                )
+            )
+
+        ]
+
+@ResetInserter()
+@CEInserter()
+class SERDES_10bits(Module):
+    def __init__(self, pad):
+        self.oe = Signal()
+        self.d = Signal(10)
+
+        # # #
+
+        o = Signal()
+        tx_bitcount = Signal(max=10)
+        tx_reg = Signal(10)
+
+        # DEBUG:
+        self.o = Signal()
+        self.comb += self.o.eq(o)
+
+        self.specials += Instance("OBUF", i_I=o, o_O=pad),
+        
+        self.sync += [
+            If(self.oe,
+                # send LSB first
+                o.eq(tx_reg[0]),
+                tx_reg.eq(Cat(tx_reg[1:], 0)),
+                tx_bitcount.eq(tx_bitcount + 1),   
+
+                If(tx_bitcount == 9,
+                    tx_bitcount.eq(0),
+                    tx_reg.eq(self.d),
+                ),
+            ).Else(
+                o.eq(0),
+                tx_bitcount.eq(0),
+            )
+        ]
+
+class Debug_buffer(Module,AutoCSR):
+    def __init__(self, layout):
+        self.sink_stb = Signal()
+        self.sink_ack = Signal()
+        self.sink_data = Signal(8)
+        self.sink_k = Signal()
+
+        # # #
+
+        self.submodules.buf_out = buf_out = stream.SyncFIFO(layout, 512)
+
+        self.sync += [
+            buf_out.sink.stb.eq(self.sink_stb),
+            self.sink_ack.eq(buf_out.sink.ack),
+            buf_out.sink.data.eq(self.sink_data),
+            buf_out.sink.k.eq(self.sink_k),
+        ]
+
+        self.inc = CSR()
+        self.dout_pak = CSRStatus(8)
+        self.kout_pak = CSRStatus()
+        self.dout_valid = CSRStatus()
+
+        self.sync += [
+            # output
+            buf_out.source.ack.eq(self.inc.re),
+            self.dout_pak.status.eq(buf_out.source.data),
+            self.kout_pak.status.eq(buf_out.source.k),
+            self.dout_valid.status.eq(buf_out.source.stb),
+        ]
+
+
+class Transmitter(Module, AutoCSR):
+    def __init__(self, pad, sys_clk_freq, debug_sma, pmod_pads):
+        self.bitrate2x_enable = Signal()
+        self.clk_reset = Signal()
+        self.tx_enable = Signal()
+
+        # # #
+
+        self.sink = stream.Endpoint(char_layout)
+
+        self.submodules.cg = cg = UpConn_ClockGen(sys_clk_freq)
+        self.submodules.encoder = encoder = SingleEncoder(True)
+        self.submodules.debug_buf = debug_buf = Debug_buffer(char_layout)
+
+        oe = Signal()
+        self.sync += [
+            If(self.tx_enable,
+                self.sink.ack.eq(0),
+
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                If(cg.clk,
+                    oe.eq(1),
+                    encoder.disp_in.eq(encoder.disp_out),
+                    self.sink.ack.eq(1),
+                    encoder.d.eq(self.sink.data),
+                    encoder.k.eq(self.sink.k),
+
+                    # DEBUG:
+                    If(debug_buf.sink_ack,
+                        debug_buf.sink_stb.eq(1),
+                        debug_buf.sink_data.eq(self.sink.data),
+                        debug_buf.sink_k.eq(self.sink.k),
+                    )
+                )
+            ).Else(
+                # DEBUG:
+                debug_buf.sink_stb.eq(0),
+
+                # no backpressure
+                self.sink.ack.eq(1),
+                oe.eq(0),
+            )
+        ]
+
+        self.submodules.serdes = serdes = SERDES_10bits(pad)
+
+        self.comb += [
+            cg.reset.eq(self.clk_reset),
+            cg.freq2x_enable.eq(self.bitrate2x_enable),
+
+            serdes.reset.eq(self.clk_reset),
+            serdes.ce.eq(cg.clk_10x),
+            serdes.d.eq(encoder.output),
+            serdes.oe.eq(oe),
+        ]
+
+class CXP_UpConn_PHYS(Module, AutoCSR):
+    def __init__(self, pads, sys_clk_freq, debug_sma, pmod_pads):
+        self.clk_reset = CSR()
+        self.bitrate2x_enable = CSRStorage()
+        self.tx_enable = CSRStorage()
+
+        # # #
+
+
+        self.tx_phys = []
+        for i, pad in enumerate(pads):
+            tx = Transmitter(pad, sys_clk_freq, debug_sma, pmod_pads)
+            self.tx_phys.append(tx)
+            setattr(self.submodules, "tx"+str(i), tx)
+            self.sync += [
+                tx.clk_reset.eq(self.clk_reset.re),
+                tx.bitrate2x_enable.eq(self.bitrate2x_enable.storage),
+                tx.tx_enable.eq(self.tx_enable.storage),
+            ]

src/gateware/zc706.py

@@ -25,6 +25,8 @@ import analyzer
 import acpki
 import drtio_aux_controller
 import zynq_clocking
+import cxp_4r_fmc
+import cxp, cxp_frame_pipeline
 from config import write_csr_file, write_mem_file, write_rustc_cfg_file
 
 class SMAClkinForward(Module):
@@ -138,7 +140,7 @@ class ZC706(SoCCore):
         platform.add_extension(si5324_fmc33)
         self.comb += platform.request("si5324_33").rst_n.eq(1)
 
-        cdr_clk = Signal()
+        self.cdr_clk = Signal()
         cdr_clk_buf = Signal()
         si5324_out = platform.request("si5324_clkout")
         platform.add_period_constraint(si5324_out.p, 8.0)
@@ -146,11 +148,11 @@ class ZC706(SoCCore):
             Instance("IBUFDS_GTE2",
                 i_CEB=0,
                 i_I=si5324_out.p, i_IB=si5324_out.n,
-                o_O=cdr_clk,
+                o_O=self.cdr_clk,
                 p_CLKCM_CFG="TRUE",
                 p_CLKRCV_TRST="TRUE",
                 p_CLKSWING_CFG=3),
-            Instance("BUFG", i_I=cdr_clk, o_O=cdr_clk_buf)
+            Instance("BUFG", i_I=self.cdr_clk, o_O=cdr_clk_buf)
         ]
         self.config["HAS_SI5324"] = None
         self.config["SI5324_AS_SYNTHESIZER"] = None
@@ -652,6 +654,118 @@ class _NIST_QC2_RTIO:
         self.add_rtio(rtio_channels)
 
 
+class CXP_FMC():
+    """
+    CoaXpress FMC with 4 CXP channel and 1 SMA trigger
+    """
+    def __init__(self):
+        platform = self.platform
+        platform.add_extension(cxp_4r_fmc.fmc_adapter_io)
+        platform.add_extension(leds_fmc33)
+
+        debug_sma = [
+            ("user_sma_clock_33", 0,
+                Subsignal("p_tx", Pins("AD18"), IOStandard("LVCMOS33")),
+                Subsignal("n_rx", Pins("AD19"), IOStandard("LVCMOS33")),
+            ),
+        ]
+
+        pmod1_33 = [
+            ("pmod1_33", 0, Pins("AJ21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 1, Pins("AK21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 2, Pins("AB21"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 3, Pins("AB16"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 4, Pins("Y20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 5, Pins("AA20"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 6, Pins("AC18"), IOStandard("LVCMOS33")),
+            ("pmod1_33", 7, Pins("AC19"), IOStandard("LVCMOS33")),
+        ]
+
+        platform.add_extension(debug_sma)
+        platform.add_extension(pmod1_33)
+        debug_sma_pad = platform.request("user_sma_clock_33") 
+        pmod_pads = [platform.request("pmod1_33", i) for i in range(8)]
+
+        clk_freq = 125e6
+
+        links = 4
+        cxp_downconn_pads = [platform.request("CXP_HS", i) for i in range(links)]
+        cxp_upconn_pads = [platform.request("CXP_LS", i) for i in range(links)]
+
+
+        self.submodules.cxp_phys = cxp_phys = cxp.CXP_PHYS(
+            refclk=self.cdr_clk,
+            upconn_pads=cxp_upconn_pads,
+            downconn_pads=cxp_downconn_pads,
+            sys_clk_freq=clk_freq,
+            debug_sma=debug_sma_pad,
+            pmod_pads = pmod_pads
+        )
+        self.csr_devices.append("cxp_phys")
+
+
+        rtio_channels = []
+        cxp_csr_group = []
+        cxp_mem_group = []
+        cxp_downconns = []
+        for i, (tx, rx) in enumerate(zip(cxp_phys.upconn.tx_phys, cxp_phys.downconn.rx_phys)):
+            cxp_name = "cxp" + str(i)
+
+            if i == 0:
+                cxp_interface = cxp.CXP_Master(tx, rx, debug_sma_pad, pmod_pads)
+
+                # Add rtlink for Master Connection only
+                print("CoaXPress at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+                rtio_channels.append(rtio.Channel.from_phy(cxp_interface))
+            else:
+                cxp_interface = cxp.CXP_Extension(tx, rx, debug_sma_pad, pmod_pads)
+
+            setattr(self.submodules, cxp_name, cxp_interface)
+            self.csr_devices.append(cxp_name)
+            cxp_csr_group.append(cxp_name)
+
+            cxp_downconns.append(cxp_interface.get_rx_downconn())
+
+            # Add memory group
+
+            mem_name = "cxp_" + str(i) + "_mem"
+            cxp_mem_group.append(mem_name)
+            mem_size = cxp_interface.get_mem_size()
+            # upper half is tx while lower half is rx
+            memory_address = self.axi2csr.register_port(cxp_interface.get_tx_port(), mem_size)
+            self.axi2csr.register_port(cxp_interface.get_rx_port(), mem_size)
+            self.add_memory_region(mem_name, self.mem_map["csr"] + memory_address, mem_size * 2)
+
+        self.add_memory_group("cxp_mem", cxp_mem_group)
+        self.add_csr_group("cxp", cxp_csr_group)
+
+        self.submodules.cxp_frame_pipeline = cxp.CXP_Frame_Pipeline(cxp_downconns, pmod_pads)
+        self.csr_devices.append("cxp_frame_pipeline")
+
+       
+
+        # max freq of cxp_gtx_rx = linerate/internal_datawidth = 12.5Gbps/40 = 312.5MHz
+        # zc706 use speed grade 2 which only support up to 10.3125Gbps (4ns)
+        # pushing to 12.5Gbps (3.2ns) will result in Pulse width violation but setup/hold times are met
+        rx = cxp_phys.downconn.rx_phys[0]
+        platform.add_period_constraint(rx.gtx.cd_cxp_gtx_tx.clk, 3.2)
+        platform.add_period_constraint(rx.gtx.cd_cxp_gtx_rx.clk, 3.2)
+        # constraint the CLK path 
+        platform.add_false_path_constraints(self.sys_crg.cd_sys.clk, rx.gtx.cd_cxp_gtx_tx.clk, rx.gtx.cd_cxp_gtx_rx.clk)
+
+        # FIXME remove this placeholder RTIO channel
+        # There are too few RTIO channels and cannot be compiled (adr width issue of the lane distributor)
+        # see https://github.com/m-labs/artiq/pull/2158 for similar issue
+        print("USER LED at RTIO channel 0x{:06x}".format(len(rtio_channels)))
+        phy = ttl_simple.Output(self.platform.request("user_led_33", 0))
+        self.submodules += phy
+        rtio_channels.append(rtio.Channel.from_phy(phy))
+        self.config["HAS_RTIO_LOG"] = None
+        rtio_channels.append(rtio.LogChannel())
+
+        self.config["RTIO_LOG_CHANNEL"] = len(rtio_channels)
+        self.add_rtio(rtio_channels)
+
 class NIST_CLOCK(ZC706, _NIST_CLOCK_RTIO):
     def __init__(self, acpki, drtio100mhz):
         ZC706.__init__(self, acpki)
@@ -684,8 +798,13 @@ class NIST_QC2_Satellite(_SatelliteBase, _NIST_QC2_RTIO):
         _SatelliteBase.__init__(self, acpki, drtio100mhz)
         _NIST_QC2_RTIO.__init__(self)
 
+class CXP_Demo(ZC706, CXP_FMC):
+    def __init__(self, acpki, drtio100mhz):
+        ZC706.__init__(self, acpki)
+        CXP_FMC.__init__(self)
+
 VARIANTS = {cls.__name__.lower(): cls for cls in [NIST_CLOCK, NIST_CLOCK_Master, NIST_CLOCK_Satellite,
-                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite]}
+                                                  NIST_QC2, NIST_QC2_Master, NIST_QC2_Satellite, CXP_Demo]}
 
 def main():
     parser = argparse.ArgumentParser(

src/libboard_artiq/Cargo.toml.tpl

@@ -24,6 +24,7 @@ core_io = { version = "0.1", features = ["collections"] }
 embedded-hal = "0.2"
 nb = "1.0"
 void = { version = "1", default-features = false }
+byteorder = { version = "1.3", default-features = false }
 
 io = { path = "../libio", features = ["byteorder"] }
 libboard_zynq = { path = "@@ZYNQ_RS@@/libboard_zynq" }

src/libboard_artiq/src/cxp.rs

@@ -0,0 +1,388 @@
+use core::{fmt, result::Result};
+
+use embedded_hal::blocking::delay::DelayMs;
+use libboard_zynq::timer::GlobalTimer;
+use log::{info, warn};
+
+use crate::{cxp_ctrl::{read_u32, read_u64, reset_tag, send_test_packet, write_bytes_no_ack, write_u32, write_u64},
+            cxp_phys::{self, CXP_CHANNELS, CXP_SPEED},
+            cxp_proto::Error as ProtoError,
+            pl::csr::{cxp_frame_pipeline, CXP}};
+
+// Bootstrap registers address
+const STANDARD: u32 = 0x0000;
+const REVISION: u32 = 0x0004;
+const CONNECTION_RESET: u32 = 0x4000;
+const DEVICE_CONNECTION_ID: u32 = 0x4004;
+const MASTER_HOST_CONNECTION_ID: u32 = 0x4008;
+
+const CONTROL_PACKET_SIZE_MAX: u32 = 0x400C;
+const STREAM_PACKET_SIZE_MAX: u32 = 0x4010;
+const CONNECTION_CFG: u32 = 0x4014;
+const CONNECTION_CFG_DEFAULT: u32 = 0x4018;
+
+const TESTMODE: u32 = 0x401C;
+const TEST_ERROR_COUNT_SELECTOR: u32 = 0x4020;
+const TEST_ERROR_COUNT: u32 = 0x4024;
+const TEST_PACKET_COUNT_TX: u32 = 0x4028;
+const TEST_PACKET_COUNT_RX: u32 = 0x4030;
+
+const VERSION_SUPPORTED: u32 = 0x4044;
+const VERSION_USED: u32 = 0x4048;
+
+// Setup const
+const MAX_STREAM_PAK_SIZE: u32 = 0x800; // 2 KiB
+const TX_TEST_CNT: u8 = 10;
+pub const MASTER_CHANNEL: u8 = 0;
+const HOST_CONNECTION_ID: u32 = 0xC001C0DE; // TODO: rename this
+
+#[derive(Debug)]
+pub enum Error {
+    CameraNotDetected,
+    ConnectionLost,
+    UnstableDownConn,
+    UnstableUpConn,
+    UnsupportedSpeed(u32),
+    UnsupportedTopology,
+    UnsupportedVersion,
+    Protocol(ProtoError),
+}
+
+impl From<ProtoError> for Error {
+    fn from(value: ProtoError) -> Error {
+        Error::Protocol(value)
+    }
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            &Error::CameraNotDetected => write!(f, "CameraNotDetected"),
+            &Error::ConnectionLost => write!(f, "ConnectionLost Some active channels cannot be detected"),
+            &Error::UnstableDownConn => write!(f, "UnstableDownConn DownConnection test failed"),
+            &Error::UnstableUpConn => write!(f, "UnstableUpConn UpConnection test failed"),
+            &Error::UnsupportedSpeed(linerate_code) => write!(
+                f,
+                "UnsupportedSpeed {:#X} linerate code is not supported",
+                linerate_code
+            ),
+            &Error::UnsupportedTopology => write!(
+                f,
+                "UnsupportedTopology CH#1 should be the master channel while CH#2-4 should be connected to extension \
+                 #1-3 respectively"
+            ),
+            &Error::UnsupportedVersion => write!(
+                f,
+                "UnsupportedVersion Cannot find a compatible protocol version between the grabber & camera"
+            ),
+            &Error::Protocol(ref err) => write!(f, "ProtocolError {}", err),
+        }
+    }
+}
+
+pub fn setup() -> Result<bool, Error> {
+    // assume timer was initialized successfully
+    let mut timer = unsafe { GlobalTimer::get() };
+    camera_setup(&mut timer)
+}
+
+fn scan_active_channels() -> u8 {
+    let mut active_channels: u8 = 0;
+    for ch in 0..CXP_CHANNELS {
+        if unsafe { (CXP[ch as usize].downconn_rx_ready_read)() } == 1 {
+            info!("ch#{} is up <---------------------------------", ch);
+            active_channels += 1;
+        }
+    }
+    active_channels
+}
+
+fn discover_camera(timer: &mut GlobalTimer) -> Result<(), Error> {
+    // Section 7.6 (CXP-001-2021)
+    // 1.25Gbps (CXP_1) and 3.125Gbps (CXP_3) are the discovery rate
+    // both linerate need to be checked as camera only support ONE of discovery rates
+    for speed in [CXP_SPEED::CXP_1, CXP_SPEED::CXP_3].iter() {
+        cxp_phys::change_linerate(*speed);
+
+        // Section 12.1.2 (CXP-001-2021)
+        // send ConnectionReset on all channels -> wait 200ms -> scan for active channels
+        for ch in 0..CXP_CHANNELS {
+            write_bytes_no_ack(ch, CONNECTION_RESET, &1_u32.to_be_bytes(), false)?;
+        }
+        timer.delay_ms(200);
+
+        if scan_active_channels() > 0 {
+            return Ok(());
+        }
+    }
+    Err(Error::CameraNotDetected)
+}
+
+fn check_master_channel() -> Result<(), Error> {
+    if read_u32(MASTER_CHANNEL, DEVICE_CONNECTION_ID, false)? == 0 {
+        Ok(())
+    } else {
+        warn!(
+            "Channel #{} is not connected to master channel of the camera",
+            MASTER_CHANNEL
+        );
+        Err(Error::UnsupportedTopology)
+    }
+}
+
+fn check_connection_topology(active_channels: u8) -> Result<(), Error> {
+    // only the simple topology MASTER:ch0, extension:ch1,2,3 is supported right now
+    for ch in 0..active_channels {
+        if read_u32(ch, DEVICE_CONNECTION_ID, false)? != ch as u32 {
+            warn!("Channel #{} is not connected to the right port of the camera", ch);
+            return Err(Error::UnsupportedTopology);
+        };
+        match ch {
+            0 => info!("CHANNEL #{} is active - master connection", ch),
+            _ => info!("CHANNEL #{} is active - extension connection", ch),
+        }
+    }
+    Ok(())
+}
+
+fn negotiate_active_channels(timer: &mut GlobalTimer) -> Result<u8, Error> {
+    let mut available_chs = read_u32(MASTER_CHANNEL, CONNECTION_CFG_DEFAULT, false)? >> 16;
+    available_chs = available_chs.min(CXP_CHANNELS as u32);
+
+    // activate channels on camera but preserve the discovery linerate
+    let current_cfg = read_u32(MASTER_CHANNEL, CONNECTION_CFG, false)?;
+    write_u32(
+        MASTER_CHANNEL,
+        CONNECTION_CFG,
+        current_cfg & 0xFFFF | available_chs << 16,
+        false,
+    )?;
+
+    timer.delay_ms(200);
+    let active_channels = scan_active_channels();
+    check_connection_topology(active_channels)?;
+
+    if available_chs > active_channels as u32 {
+        info!(
+            "Only detected {} channel(s), disabling excess channels on camera",
+            active_channels
+        );
+        write_u32(
+            MASTER_CHANNEL,
+            CONNECTION_CFG,
+            current_cfg & 0xFFFF | ((active_channels as u32) << 16),
+            false,
+        )?;
+
+        timer.delay_ms(200);
+        // check no active channels are down after the cfg change
+        if active_channels != scan_active_channels() {
+            return Err(Error::ConnectionLost);
+        }
+    }
+    Ok(active_channels)
+}
+
+fn set_host_connection_id() -> Result<(), Error> {
+    // TODO: not mandatory??
+    write_u32(MASTER_CHANNEL, MASTER_HOST_CONNECTION_ID, HOST_CONNECTION_ID, false)?;
+    let reg = read_u32(MASTER_CHANNEL, CONNECTION_CFG, false)?;
+    info!("host connection id set as = {}", reg);
+    Ok(())
+}
+
+fn negotiate_cxp_version() -> Result<bool, Error> {
+    let rev = read_u32(MASTER_CHANNEL, REVISION, false)?;
+
+    let mut major_rev: u32 = rev >> 16;
+    let mut minor_rev: u32 = rev & 0xFF;
+    info!("Camera's CXP revision is {}.{}", major_rev, minor_rev);
+
+    // Section 12.1.4 (CXP-001-2021)
+    // For CXP 2.0 and onward, Host need to check the VersionSupported register to determine
+    // the highest common version that supported by both device & host
+    if major_rev >= 2 {
+        let reg = read_u32(MASTER_CHANNEL, VERSION_SUPPORTED, false)?;
+
+        if ((reg >> 3) & 1) == 1 {
+            major_rev = 2;
+            minor_rev = 1;
+        } else if ((reg >> 2) & 1) == 1 {
+            major_rev = 2;
+            minor_rev = 0;
+        } else {
+            return Err(Error::UnsupportedVersion);
+        }
+
+        write_u32(MASTER_CHANNEL, VERSION_USED, major_rev << 16 | minor_rev, false)?;
+    }
+    info!(
+        "Camera supports CXP {}.{}, using CXP {}.{} protcol now",
+        major_rev, minor_rev, major_rev, minor_rev
+    );
+
+    Ok(major_rev >= 2)
+}
+
+fn negotiate_pak_max_size(with_tag: bool) -> Result<(), Error> {
+    let reg = read_u32(MASTER_CHANNEL, CONTROL_PACKET_SIZE_MAX, with_tag)?;
+    info!("Max CTRL PAK size = {:#010X}", reg);
+
+    let reg = read_u32(MASTER_CHANNEL, STREAM_PACKET_SIZE_MAX, with_tag)?;
+    info!("Max STREAM PAK size = {:#010X}", reg);
+    // TODO: set stream packet size
+    write_u32(MASTER_CHANNEL, STREAM_PACKET_SIZE_MAX, MAX_STREAM_PAK_SIZE, with_tag)?;
+    let reg = read_u32(MASTER_CHANNEL, STREAM_PACKET_SIZE_MAX, with_tag)?;
+    info!("Max STREAM PAK size = {:#010X}", reg);
+    Ok(())
+}
+
+fn check_magic_word() -> Result<(), Error> {
+    let reg = read_u32(MASTER_CHANNEL, STANDARD, true)?;
+    info!("CoaXPress magic WORD = {:#010X} !!!", reg);
+    Ok(())
+}
+
+fn decode_cxp_speed(linerate_code: u32) -> Option<CXP_SPEED> {
+    match linerate_code {
+        0x28 => Some(CXP_SPEED::CXP_1),
+        0x30 => Some(CXP_SPEED::CXP_2),
+        0x38 => Some(CXP_SPEED::CXP_3),
+        0x40 => Some(CXP_SPEED::CXP_5),
+        0x48 => Some(CXP_SPEED::CXP_6),
+        0x50 => Some(CXP_SPEED::CXP_10),
+        0x58 => Some(CXP_SPEED::CXP_12),
+        _ => None,
+    }
+}
+
+fn set_operation_linerate(active_channels: u8, with_tag: bool, timer: &mut GlobalTimer) -> Result<(), Error> {
+    let current_cfg = read_u32(MASTER_CHANNEL, CONNECTION_CFG, with_tag)?;
+    info!("Current connection cfg = {:#010X}", current_cfg);
+
+    let recommended_linerate_code = read_u32(MASTER_CHANNEL, CONNECTION_CFG_DEFAULT, with_tag)? & 0xFFFF;
+    info!("recommended_linerate_code = {:#010X}", recommended_linerate_code);
+
+    if let Some(speed) = decode_cxp_speed(recommended_linerate_code) {
+        // preserve the number of active channels
+        write_u32(
+            MASTER_CHANNEL,
+            CONNECTION_CFG,
+            current_cfg & 0xFFFF0000 | recommended_linerate_code,
+            with_tag,
+        )?;
+
+        cxp_phys::change_linerate(speed);
+        timer.delay_ms(200);
+
+        // check no active channels are down after linerate change
+        if scan_active_channels() == active_channels {
+            Ok(())
+        } else {
+            Err(Error::ConnectionLost)
+        }
+    } else {
+        Err(Error::UnsupportedSpeed(recommended_linerate_code))
+    }
+}
+
+fn test_counter_reset(channel: u8, with_tag: bool) -> Result<(), Error> {
+    unsafe { (CXP[channel as usize].downconn_bootstrap_test_counts_reset_write)(1) };
+    write_u32(MASTER_CHANNEL, TEST_ERROR_COUNT_SELECTOR, channel as u32, with_tag)?;
+    write_u32(MASTER_CHANNEL, TEST_ERROR_COUNT, 0, with_tag)?;
+    write_u64(MASTER_CHANNEL, TEST_PACKET_COUNT_TX, 0, with_tag)?;
+    write_u64(MASTER_CHANNEL, TEST_PACKET_COUNT_RX, 0, with_tag)?;
+    Ok(())
+}
+
+fn verify_test_result(channel: u8, with_tag: bool) -> Result<(), Error> {
+    write_u32(MASTER_CHANNEL, TEST_ERROR_COUNT_SELECTOR, channel as u32, with_tag)?;
+
+    // Section 9.9.3 (CXP-001-2021)
+    // verify grabber -> camera connection test result
+    if read_u64(MASTER_CHANNEL, TEST_PACKET_COUNT_RX, with_tag)? != TX_TEST_CNT as u64 {
+        return Err(Error::UnstableUpConn);
+    };
+    if read_u32(MASTER_CHANNEL, TEST_ERROR_COUNT, with_tag)? > 0 {
+        return Err(Error::UnstableUpConn);
+    };
+
+    // Section 9.9.4 (CXP-001-2021)
+    // verify camera -> grabber connection test result
+    let camera_test_pak_cnt = read_u64(MASTER_CHANNEL, TEST_PACKET_COUNT_TX, true)?;
+    unsafe {
+        if (CXP[channel as usize].downconn_bootstrap_test_packet_counter_read)() != camera_test_pak_cnt as u16 {
+            info!(
+                "CHANNEL #{} test packet cnt = {}",
+                channel,
+                (CXP[channel as usize].downconn_bootstrap_test_packet_counter_read)()
+            );
+            return Err(Error::UnstableDownConn);
+        };
+        if (CXP[channel as usize].downconn_bootstrap_test_error_counter_read)() > 0 {
+            info!(
+                "CHANNEL #{} test packet error cnt = {}",
+                channel,
+                (CXP[channel as usize].downconn_bootstrap_test_error_counter_read)()
+            );
+            return Err(Error::UnstableDownConn);
+        };
+    };
+    info!("CHANNEL #{} pass testing", channel);
+    Ok(())
+}
+
+fn test_channels_stability(active_channels: u8, with_tag: bool, timer: &mut GlobalTimer) -> Result<(), Error> {
+    // let active_channels = active_channels as usize;
+    for ch in 0..active_channels {
+        test_counter_reset(ch, with_tag)?;
+    }
+
+    // grabber -> camera connection test
+    for ch in 0..active_channels {
+        for _ in 0..TX_TEST_CNT {
+            send_test_packet(ch)?;
+            // sending the whole test sequence @ 20.833Mbps will take a minimum of 1.972ms
+            // and leave some room to send IDLE word
+            timer.delay_ms(2);
+        }
+    }
+
+    // camera -> grabber connection test
+    // enabling the TESTMODE on master channel will send test packets on all channels
+    // and ctrl packet write overhead is used as a delay
+    write_u32(MASTER_CHANNEL, TESTMODE, 1, with_tag)?;
+    write_u32(MASTER_CHANNEL, TESTMODE, 0, with_tag)?;
+
+    for ch in 0..active_channels {
+        verify_test_result(ch, with_tag)?;
+    }
+
+    Ok(())
+}
+
+fn camera_setup(timer: &mut GlobalTimer) -> Result<bool, Error> {
+    reset_tag();
+    discover_camera(timer)?;
+    check_master_channel()?;
+
+    let active_channels = negotiate_active_channels(timer)?;
+    set_host_connection_id()?;
+    let cxp_v2_or_greater = negotiate_cxp_version()?;
+
+    negotiate_pak_max_size(cxp_v2_or_greater)?;
+    set_operation_linerate(active_channels, cxp_v2_or_greater, timer)?;
+
+    // DEBUG: print
+    check_magic_word()?;
+
+    test_channels_stability(active_channels, cxp_v2_or_greater, timer)?;
+
+    // unsafe{
+    //     // don't set two identical routingid, the router cannot handle it
+    //     // it can handle it after adding the priority decoder
+    //     cxp_frame_pipeline::buffer_1_routingid_write(0x00);
+    // }
+
+    Ok(cxp_v2_or_greater)
+}

src/libboard_artiq/src/cxp_ctrl.rs

@@ -0,0 +1,261 @@
+use core::slice;
+
+use byteorder::{ByteOrder, NetworkEndian};
+use io::Cursor;
+use libboard_zynq::{println, time::Milliseconds, timer::GlobalTimer};
+
+use crate::{cxp_proto::{print_packet, DownConnPacket, Error, UpConnPacket, DATA_MAXSIZE},
+            mem::mem::CXP_MEM,
+            pl::csr::CXP};
+
+const BUF_LEN: usize = 0x800;
+const TRANSMISSION_TIMEOUT: u64 = 200;
+
+fn packet_pending(channel: u8) -> bool {
+    unsafe { (CXP[channel as usize].downconn_pending_packet_read)() == 1 }
+}
+
+fn receive(channel: u8) -> Result<Option<DownConnPacket>, Error> {
+    if packet_pending(channel) {
+        let channel = channel as usize;
+        unsafe {
+            let read_buffer_ptr = (CXP[channel].downconn_read_ptr_read)() as usize;
+            println!("buffer ptr = {}", read_buffer_ptr);
+            let ptr = (CXP_MEM[channel].base + CXP_MEM[channel].size / 2 + read_buffer_ptr * BUF_LEN) as *mut u32;
+
+            let mut reader = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+            let packet_type = (CXP[channel].downconn_packet_type_read)();
+            println!("packet_type = {}", packet_type);
+            // DEBUG:
+            // println!("RX MEM before reading");
+            // print_packet(&reader.get_ref()[0..40]);
+
+            let packet = DownConnPacket::read_from(&mut reader, packet_type);
+            println!("{:X?}", packet);
+
+            (CXP[channel].downconn_pending_packet_write)(1);
+            Ok(Some(packet?))
+        }
+    } else {
+        Ok(None)
+    }
+}
+
+fn receive_timeout(channel: u8, timeout_ms: u64) -> Result<DownConnPacket, Error> {
+    // assume timer was initialized successfully
+    let timer = unsafe { GlobalTimer::get() };
+    let limit = timer.get_time() + Milliseconds(timeout_ms);
+    while timer.get_time() < limit {
+        match receive(channel)? {
+            None => (),
+            Some(packet) => return Ok(packet),
+        }
+    }
+    Err(Error::TimedOut)
+}
+
+fn send_data_packet(channel: u8, packet: &UpConnPacket) -> Result<(), Error> {
+    // assume upconn tx is enabled
+    let channel = channel as usize;
+    unsafe {
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        let ptr = CXP_MEM[channel].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+
+        packet.write_to(&mut writer)?;
+        // DEBUG:
+        // println!("TX MEM after writing");
+        // print_packet(&writer.get_ref()[0..40]);
+
+        (CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
+        (CXP[channel].upconn_bootstrap_tx_write)(1);
+    }
+
+    Ok(())
+}
+
+pub fn send_test_packet(channel: u8) -> Result<(), Error> {
+    // assume upconn tx is enabled
+    let channel = channel as usize;
+    unsafe {
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        (CXP[channel].upconn_bootstrap_tx_testseq_write)(1);
+    }
+    Ok(())
+}
+
+//
+//
+// DEBUG:
+//
+//
+pub fn downconn_debug_mem_print(channel: u8) {
+    unsafe {
+        let ptr = CXP_MEM[channel as usize].base as *mut u32;
+        let arr = slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN * 4);
+        print_packet(arr);
+    }
+}
+
+pub fn print_decode_error(channel: u8) {
+    unsafe {
+        println!(
+            "CH#{} Decode error = {}",
+            channel,
+            (CXP[channel as usize].downconn_bootstrap_decoder_err_read)()
+        );
+    }
+}
+
+//
+//
+// CTRL packet
+//
+//
+
+// Section 9.6.1.2 (CXP-001-2021)
+// CTRL packet need to be tagged for CXP 2.0 or greater
+static mut TAG: u8 = 0;
+
+pub fn reset_tag() {
+    unsafe { TAG = 0 }
+}
+
+fn increment_tag() {
+    unsafe { TAG = TAG.wrapping_add(1) };
+}
+
+fn check_tag(tag: Option<u8>) -> Result<(), Error> {
+    unsafe {
+        if tag.is_some() && tag != Some(TAG) {
+            Err(Error::TagMismatch)
+        } else {
+            Ok(())
+        }
+    }
+}
+
+fn check_length(length: u32) -> Result<(), Error> {
+    if length > DATA_MAXSIZE as u32 || length == 0 {
+        Err(Error::LengthOutOfRange)
+    } else {
+        Ok(())
+    }
+}
+
+fn process_ack_packet(channel: u8, timeout: u64) -> Result<(), Error> {
+    match receive_timeout(channel, timeout) {
+        Ok(DownConnPacket::CtrlAck { tag }) => {
+            check_tag(tag)?;
+            Ok(())
+        }
+        Ok(DownConnPacket::CtrlDelay { tag, time }) => {
+            check_tag(tag)?;
+
+            // info!("delaying by {} ms ....", time);
+            process_ack_packet(channel, time as u64)
+        }
+        Ok(_) => Err(Error::UnexpectedReply),
+        Err(e) => Err(e),
+    }
+}
+
+fn process_reply_packet(channel: u8, timeout: u64, expected_length: u32) -> Result<[u8; DATA_MAXSIZE], Error> {
+    match receive_timeout(channel, timeout) {
+        Ok(DownConnPacket::CtrlReply { tag, length, data }) => {
+            check_tag(tag)?;
+
+            if length != expected_length {
+                return Err(Error::UnexpectedReply);
+            };
+
+            Ok(data)
+        }
+        Ok(DownConnPacket::CtrlDelay { tag, time }) => {
+            check_tag(tag)?;
+
+            // info!("delaying by {} ms ....", time);
+            process_reply_packet(channel, time as u64, expected_length)
+        }
+        Ok(_) => Err(Error::UnexpectedReply),
+        Err(e) => Err(e),
+    }
+}
+
+pub fn write_bytes_no_ack(channel: u8, addr: u32, val: &[u8], with_tag: bool) -> Result<(), Error> {
+    let length = val.len() as u32;
+    check_length(length)?;
+
+    let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    data[..length as usize].clone_from_slice(val);
+
+    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
+    send_data_packet(
+        channel,
+        &UpConnPacket::CtrlWrite {
+            tag,
+            addr,
+            length,
+            data,
+        },
+    )
+}
+
+pub fn write_bytes(channel: u8, addr: u32, val: &[u8], with_tag: bool) -> Result<(), Error> {
+    write_bytes_no_ack(channel, addr, val, with_tag)?;
+    process_ack_packet(channel, TRANSMISSION_TIMEOUT)?;
+
+    // DEBUG
+    print_decode_error(channel);
+
+    if with_tag {
+        increment_tag();
+    };
+    Ok(())
+}
+
+pub fn write_u32(channel: u8, addr: u32, val: u32, with_tag: bool) -> Result<(), Error> {
+    write_bytes(channel, addr, &val.to_be_bytes(), with_tag)
+}
+
+pub fn write_u64(channel: u8, addr: u32, val: u64, with_tag: bool) -> Result<(), Error> {
+    write_bytes(channel, addr, &val.to_be_bytes(), with_tag)
+}
+
+fn read(channel: u8, addr: u32, length: u32, with_tag: bool) -> Result<(), Error> {
+    check_length(length)?;
+    let tag: Option<u8> = if with_tag { Some(unsafe { TAG }) } else { None };
+    send_data_packet(channel, &UpConnPacket::CtrlRead { tag, addr, length })
+}
+
+pub fn read_bytes(channel: u8, addr: u32, bytes: &mut [u8], with_tag: bool) -> Result<(), Error> {
+    let length = bytes.len() as u32;
+    read(channel, addr, length, with_tag)?;
+
+    let data = process_reply_packet(channel, TRANSMISSION_TIMEOUT, length)?;
+    bytes.clone_from_slice(&data[..length as usize]);
+
+    // DEBUG
+    print_decode_error(channel);
+
+    if with_tag {
+        increment_tag();
+    };
+    Ok(())
+}
+
+pub fn read_u32(channel: u8, addr: u32, with_tag: bool) -> Result<u32, Error> {
+    let mut bytes: [u8; 4] = [0; 4];
+    read_bytes(channel, addr, &mut bytes, with_tag)?;
+    let val = NetworkEndian::read_u32(&bytes);
+
+    Ok(val)
+}
+
+pub fn read_u64(channel: u8, addr: u32, with_tag: bool) -> Result<u64, Error> {
+    let mut bytes: [u8; 8] = [0; 8];
+    read_bytes(channel, addr, &mut bytes, with_tag)?;
+    let val = NetworkEndian::read_u64(&bytes);
+
+    Ok(val)
+}

src/libboard_artiq/src/cxp_downconn.rs

@@ -0,0 +1,89 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::{println, timer::GlobalTimer};
+use log::info;
+
+use crate::{cxp_phys, pl::csr::CXP};
+
+pub fn loopback_testing(channel: usize, timer: &mut GlobalTimer, speed: cxp_phys::CXP_SPEED) {
+    println!("==============================================================================");
+    cxp_phys::change_linerate(speed);
+
+    unsafe {
+        info!("waiting for tx&rx setup...");
+        timer.delay_us(50_000);
+        info!(
+            "tx_phaligndone = {} | rx_phaligndone = {}",
+            (CXP[channel].downconn_txinit_phaligndone_read)(),
+            (CXP[channel].downconn_rxinit_phaligndone_read)(),
+        );
+
+        // enable txdata tranmission thought MGTXTXP, required by PMA loopback
+        // (CXP[channel].downconn_txenable_write)(1);
+
+        info!("waiting for rx to align...");
+        while (CXP[channel].downconn_rx_ready_read)() != 1 {}
+        info!("rx ready!");
+
+        // cxp_proto::downconn_send_test_packet(channel);
+
+        // FIXME: why test + trig ack doesn't work well for rx??
+        // cxp_proto::downconn_debug_send_trig_ack(channel);
+
+        // const DATA_MAXSIZE: usize = 253;
+        // let data_size = 4; // no. of bytes
+
+        // let data: u32 = 0xDADA as u32;
+        // let mut data_slice: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+        // data_slice[..4].clone_from_slice(&data.to_be_bytes());
+        // cxp_proto::downconn_debug_send(
+        //     channel,
+        //     &cxp_proto::UpConnPacket::Event {
+        //         conn_id: 0x1234_5678_u32,
+        //         packet_tag: 0x69_u8,
+        //         length: data_size + 3,
+        //         event_size: data_size,
+        //         namespace: 0x02_u8,
+        //         event_id: 0x00_6969u16,
+        //         timestamp: 0x1234_5678u64,
+        //         data: data_slice,
+        //     },
+        // )
+        // .expect("loopback gtx tx error");
+
+        // timer.delay_us(1000); // wait packet has arrive at RX async fifo
+
+        // if (CXP[channel].downconn_trigger_ack_read)() == 1 {
+        //     (CXP[channel].downconn_trigger_ack_write)(1);
+        //     info!("trig ack and cleared");
+        // }
+
+        // if (CXP[channel].downconn_bootstrap_decoder_err_read)() == 1 {
+        //     info!("!!!!!!!DECODER ERROR!!!!!!! and cleared");
+        //     (CXP[channel].downconn_bootstrap_decoder_err_write)(1);
+        // }
+
+        // info!("packet type = {:#06X}", (CXP[channel].downconn_packet_type_read)());
+
+        // // cxp_proto::receive(channel as u8).expect("loopback gtx rx error");
+        // // cxp_proto::downconn_debug_mem_print(channel);
+
+        // // DEBUG: print loopback packets
+        // const LEN: usize = 20;
+        // let mut pak_arr: [u32; LEN] = [0; LEN];
+        // let mut k_arr: [u8; LEN] = [0; LEN];
+        // let mut i: usize = 0;
+        // while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
+        //     pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
+        //     k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
+        //     // println!("received {:#04X}", pak_arr[i]);
+        //     (CXP[channel].downconn_debug_out_inc_write)(1);
+        //     i += 1;
+        //     if i == LEN {
+        //         break;
+        //     }
+        // }
+
+        // info!("rx ready = {}", (CXP[channel].downconn_rx_ready_read)());
+        // // cxp_proto::print_packetu32(&pak_arr, &k_arr);
+    }
+}

src/libboard_artiq/src/cxp_phys.rs

@@ -0,0 +1,218 @@
+use embedded_hal::prelude::_embedded_hal_blocking_delay_DelayUs;
+use libboard_zynq::timer::GlobalTimer;
+use log::info;
+
+use crate::pl::{csr, csr::CXP};
+
+pub const CXP_CHANNELS: u8 = csr::CXP_LEN as u8;
+
+#[derive(Clone, Copy, Debug)]
+#[allow(non_camel_case_types)]
+pub enum CXP_SPEED {
+    CXP_1,
+    CXP_2,
+    CXP_3,
+    CXP_5,
+    CXP_6,
+    CXP_10,
+    CXP_12,
+}
+
+pub fn setup(timer: &mut GlobalTimer) {
+    down_conn::setup(timer);
+    up_conn::setup();
+    change_linerate(CXP_SPEED::CXP_1);
+}
+
+pub fn change_linerate(speed: CXP_SPEED) {
+    info!("Changing all channels datarate to {:?}", speed);
+    down_conn::change_linerate(speed);
+    up_conn::change_linerate(speed);
+}
+
+mod up_conn {
+    use super::*;
+
+    pub fn setup() {
+        unsafe {
+            csr::cxp_phys::upconn_tx_enable_write(1);
+        }
+    }
+
+    pub fn change_linerate(speed: CXP_SPEED) {
+        unsafe {
+            match speed {
+                CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => {
+                    csr::cxp_phys::upconn_bitrate2x_enable_write(0);
+                }
+                CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => {
+                    csr::cxp_phys::upconn_bitrate2x_enable_write(1);
+                }
+            };
+            csr::cxp_phys::upconn_clk_reset_write(1);
+        }
+    }
+}
+
+mod down_conn {
+    use super::*;
+
+    pub fn setup(timer: &mut GlobalTimer) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+
+            csr::cxp_phys::downconn_gtx_start_init_write(1);
+
+            // DEBUG: printout
+            info!("waiting for rx setup...");
+            timer.delay_us(50_000);
+            for ch in 0..CXP_CHANNELS {
+                info!(
+                    "rx_phaligndone = {}",
+                    (CXP[ch as usize].downconn_rxinit_phaligndone_read)()
+                );
+            }
+        }
+    }
+
+    pub fn change_linerate(speed: CXP_SPEED) {
+        change_qpll_fb_divider(speed);
+        change_gtx_divider(speed);
+        change_cdr_cfg(speed);
+
+        unsafe {
+            csr::cxp_phys::downconn_qpll_reset_write(1);
+            info!("waiting for QPLL/CPLL to lock...");
+            while csr::cxp_phys::downconn_qpll_locked_read() != 1 {}
+            info!("QPLL locked");
+
+            csr::cxp_phys::downconn_gtx_restart_write(1);
+        }
+    }
+
+    fn change_qpll_fb_divider(speed: CXP_SPEED) {
+        let qpll_div_reg = match speed {
+            CXP_SPEED::CXP_1 | CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 | CXP_SPEED::CXP_10 => 0x0120, // FB_Divider = 80
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 | CXP_SPEED::CXP_12 => 0x0170,                    // FB_Divider = 100
+        };
+
+        // DEBUG:
+        // println!("QPLL DRP:");
+        // println!("0x36 = {:#06x}", qpll_read(0x36));
+        qpll_write(0x36, qpll_div_reg);
+        // println!("0x36 = {:#06x}", qpll_read(0x36));
+    }
+
+    fn change_gtx_divider(speed: CXP_SPEED) {
+        let div_reg = match speed {
+            CXP_SPEED::CXP_1 => 0x33,                      // RXOUT_DIV = 8
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_3 => 0x22,   // RXOUT_DIV = 4
+            CXP_SPEED::CXP_5 | CXP_SPEED::CXP_6 => 0x11,   // RXOUT_DIV = 2
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => 0x00, // RXOUT_DIV = 1
+        };
+
+        // DEBUG:
+        // println!("RX GTX DRP:");
+        for ch in 0..CXP_CHANNELS {
+            // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
+            gtx_write(ch, 0x88, div_reg);
+            // println!("channel {}, 0x88 = {:#06x}", channel, gtx_read(channel, 0x88));
+        }
+    }
+
+    fn change_cdr_cfg(speed: CXP_SPEED) {
+        struct CdrConfig {
+            pub cfg_reg0: u16, // addr = 0xA8
+            pub cfg_reg1: u16, // addr = 0xA9
+            pub cfg_reg2: u16, // addr = 0xAA
+            pub cfg_reg3: u16, // addr = 0xAB
+            pub cfg_reg4: u16, // addr = 0xAC
+        }
+
+        let cdr_cfg = match speed {
+            // when RXOUT_DIV = 8
+            CXP_SPEED::CXP_1 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1008,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV = 4
+            CXP_SPEED::CXP_2 | CXP_SPEED::CXP_5 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1010,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 2
+            CXP_SPEED::CXP_3 | CXP_SPEED::CXP_6 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1020,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x0003,
+            },
+            // when RXOUT_DIV= 1
+            CXP_SPEED::CXP_10 | CXP_SPEED::CXP_12 => CdrConfig {
+                cfg_reg0: 0x0020,
+                cfg_reg1: 0x1040,
+                cfg_reg2: 0x23FF,
+                cfg_reg3: 0x0000,
+                cfg_reg4: 0x000B,
+            },
+        };
+
+        for channel in 0..CXP_CHANNELS {
+            gtx_write(channel, 0x0A8, cdr_cfg.cfg_reg0);
+            gtx_write(channel, 0x0A9, cdr_cfg.cfg_reg1);
+            gtx_write(channel, 0x0AA, cdr_cfg.cfg_reg2);
+            gtx_write(channel, 0x0AB, cdr_cfg.cfg_reg3);
+            gtx_write(channel, 0x0AC, cdr_cfg.cfg_reg4);
+        }
+    }
+
+    #[allow(dead_code)]
+    fn gtx_read(channel: u8, address: u16) -> u16 {
+        let channel = channel as usize;
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_dread_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+            (CXP[channel].downconn_gtx_dout_read)()
+        }
+    }
+
+    fn gtx_write(channel: u8, address: u16, value: u16) {
+        let channel = channel as usize;
+        unsafe {
+            (CXP[channel].downconn_gtx_daddr_write)(address);
+            (CXP[channel].downconn_gtx_din_write)(value);
+            (CXP[channel].downconn_gtx_din_stb_write)(1);
+            while (CXP[channel].downconn_gtx_dready_read)() != 1 {}
+        }
+    }
+
+    #[allow(dead_code)]
+    fn qpll_read(address: u8) -> u16 {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_dread_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+            csr::cxp_phys::downconn_qpll_dout_read()
+        }
+    }
+
+    fn qpll_write(address: u8, value: u16) {
+        unsafe {
+            csr::cxp_phys::downconn_qpll_daddr_write(address);
+            csr::cxp_phys::downconn_qpll_din_write(value);
+            csr::cxp_phys::downconn_qpll_din_stb_write(1);
+            while csr::cxp_phys::downconn_qpll_dready_read() != 1 {}
+        }
+    }
+}

src/libboard_artiq/src/cxp_proto.rs

@@ -0,0 +1,423 @@
+use core::fmt;
+
+use byteorder::{ByteOrder, NetworkEndian};
+use core_io::{Error as IoError, Read, Write};
+use crc::crc32::checksum_ieee;
+use io::Cursor;
+use libboard_zynq::println;
+
+const EV_MAXSIZE: usize = 253;
+const CTRL_PACKET_MAXSIZE: usize = 128; // for compatibility with version1.x compliant Devices - Section 12.1.6 (CXP-001-2021)
+pub const DATA_MAXSIZE: usize =
+    CTRL_PACKET_MAXSIZE - /*packet start KCodes, data packet types, CMD, Tag, Addr, CRC, packet end KCode*/4*7;
+
+#[derive(Debug)]
+pub enum Error {
+    CorruptedPacket,
+    CtrlAckError(u8),
+    Io(IoError),
+    LengthOutOfRange,
+    TagMismatch,
+    TimedOut,
+    UnexpectedReply,
+    UnknownPacket(u8),
+}
+
+impl fmt::Display for Error {
+    fn fmt(&self, f: &mut fmt::Formatter) -> fmt::Result {
+        match self {
+            &Error::CorruptedPacket => write!(f, "CorruptedPacket Received packet fail CRC test"),
+            &Error::CtrlAckError(ref ack_code) => match ack_code {
+                0x40 => write!(f, "CtrlAckError Invalid Address"),
+                0x41 => write!(f, "CtrlAckError Invalid data for the address"),
+                0x42 => write!(f, "CtrlAckError Invalid operation code"),
+                0x43 => write!(f, "CtrlAckError Write attempted to a read-only address"),
+                0x44 => write!(f, "CtrlAckError Read attempted from a write-only address"),
+                0x45 => write!(f, "CtrlAckError Size field too large, exceed packet size limit"),
+                0x46 => write!(f, "CtrlAckError Message size is inconsistent with size field"),
+                0x47 => write!(f, "CtrlAckError Malformed packet"),
+                0x80 => write!(f, "CtrlAckError Failed CRC test in last received command"),
+                _ => write!(f, "CtrlAckError Unknown ack code {:#X}", ack_code),
+            },
+            &Error::Io(ref err) => write!(f, "IoError {:?}", err),
+            &Error::LengthOutOfRange => write!(f, "LengthOutOfRange Message Length is too long"),
+            &Error::TagMismatch => write!(f, "TagMismatch Received tag is different from the transmitted tag"),
+            &Error::TimedOut => write!(f, "MessageTimedOut"),
+            &Error::UnexpectedReply => write!(f, "UnexpectedReply"),
+            &Error::UnknownPacket(packet_type) => write!(f, "UnknownPacket with type id {:#X} ", packet_type),
+        }
+    }
+}
+
+impl From<IoError> for Error {
+    fn from(value: IoError) -> Error {
+        Error::Io(value)
+    }
+}
+
+fn get_cxp_crc(bytes: &[u8]) -> u32 {
+    // Section 9.2.2.2 (CXP-001-2021)
+    // Only Control packet need CRC32 appended in the end of the packet
+    // CoaXpress use the polynomial of IEEE-802.3 (Ethernet) CRC but the checksum calculation is different
+    (!checksum_ieee(bytes)).swap_bytes()
+}
+
+trait CxpRead {
+    fn read_u8(&mut self) -> Result<u8, Error>;
+
+    fn read_u16(&mut self) -> Result<u16, Error>;
+
+    fn read_u32(&mut self) -> Result<u32, Error>;
+
+    fn read_u64(&mut self) -> Result<u64, Error>;
+
+    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error>;
+
+    fn read_4x_u8(&mut self) -> Result<u8, Error>;
+
+    fn read_4x_u16(&mut self) -> Result<u16, Error>;
+
+    fn read_4x_u32(&mut self) -> Result<u32, Error>;
+}
+impl<Cursor: Read> CxpRead for Cursor {
+    fn read_u8(&mut self) -> Result<u8, Error> {
+        let mut bytes = [0; 1];
+        self.read_exact(&mut bytes)?;
+        Ok(bytes[0])
+    }
+
+    fn read_u16(&mut self) -> Result<u16, Error> {
+        let mut bytes = [0; 2];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u16(&bytes))
+    }
+
+    fn read_u32(&mut self) -> Result<u32, Error> {
+        let mut bytes = [0; 4];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u32(&bytes))
+    }
+
+    fn read_u64(&mut self) -> Result<u64, Error> {
+        let mut bytes = [0; 8];
+        self.read_exact(&mut bytes)?;
+        Ok(NetworkEndian::read_u64(&bytes))
+    }
+
+    fn read_exact_4x(&mut self, buf: &mut [u8]) -> Result<(), Error> {
+        for byte in buf {
+            // Section 9.2.2.1 (CXP-001-2021)
+            // decoder should immune to single bit errors when handling 4x duplicated characters
+            let a = self.read_u8()?;
+            let b = self.read_u8()?;
+            let c = self.read_u8()?;
+            let d = self.read_u8()?;
+            // vote and return majority
+            *byte = a & b & c | a & b & d | a & c & d | b & c & d;
+        }
+        Ok(())
+    }
+
+    fn read_4x_u8(&mut self) -> Result<u8, Error> {
+        let mut bytes = [0; 1];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(bytes[0])
+    }
+
+    fn read_4x_u16(&mut self) -> Result<u16, Error> {
+        let mut bytes = [0; 2];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(NetworkEndian::read_u16(&bytes))
+    }
+
+    fn read_4x_u32(&mut self) -> Result<u32, Error> {
+        let mut bytes = [0; 4];
+        self.read_exact_4x(&mut bytes)?;
+        Ok(NetworkEndian::read_u32(&bytes))
+    }
+}
+
+#[derive(Debug)]
+pub enum NameSpace {
+    GenICam,
+    DeviceSpecific,
+}
+
+#[derive(Debug)]
+pub enum DownConnPacket {
+    CtrlReply {
+        tag: Option<u8>,
+        length: u32,
+        data: [u8; DATA_MAXSIZE],
+    },
+    CtrlDelay {
+        tag: Option<u8>,
+        time: u32,
+    },
+    CtrlAck {
+        tag: Option<u8>,
+    },
+    Event {
+        conn_id: u32,
+        packet_tag: u8,
+        length: u16,
+        ev_size: u16,
+        namespace: NameSpace,
+        event_id: u16,
+        timestamp: u64,
+        ev: [u8; EV_MAXSIZE],
+    },
+}
+
+impl DownConnPacket {
+    pub fn read_from(reader: &mut Cursor<&mut [u8]>, packet_type: u8) -> Result<Self, Error> {
+        match packet_type {
+            0x03 => DownConnPacket::get_ctrl_packet(reader, false),
+            0x06 => DownConnPacket::get_ctrl_packet(reader, true),
+            0x07 => DownConnPacket::get_event_packet(reader),
+            _ => Err(Error::UnknownPacket(packet_type)),
+        }
+    }
+
+    fn get_ctrl_packet(reader: &mut Cursor<&mut [u8]>, with_tag: bool) -> Result<Self, Error> {
+        let mut tag: Option<u8> = None;
+        if with_tag {
+            tag = Some(reader.read_4x_u8()?);
+        }
+
+        let ackcode = reader.read_4x_u8()?;
+
+        match ackcode {
+            0x00 | 0x04 => {
+                let length = reader.read_u32()?;
+                let mut data: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+                reader.read(&mut data[0..length as usize])?;
+
+                let checksum = get_cxp_crc(&reader.get_ref()[0..reader.position()]);
+                if reader.read_u32()? != checksum {
+                    return Err(Error::CorruptedPacket);
+                }
+
+                if ackcode == 0x00 {
+                    return Ok(DownConnPacket::CtrlReply { tag, length, data });
+                } else {
+                    return Ok(DownConnPacket::CtrlDelay {
+                        tag,
+                        time: NetworkEndian::read_u32(&data[..4]),
+                    });
+                }
+            }
+            0x01 => return Ok(DownConnPacket::CtrlAck { tag }),
+            _ => return Err(Error::CtrlAckError(ackcode)),
+        }
+    }
+
+    fn get_event_packet(reader: &mut Cursor<&mut [u8]>) -> Result<Self, Error> {
+        let conn_id = reader.read_4x_u32()?;
+        let packet_tag = reader.read_4x_u8()?;
+        let length = reader.read_4x_u16()?;
+
+        let ev_size = reader.read_u16()?;
+        if ev_size + 3 != length {
+            println!("length mismatch");
+            return Err(Error::CorruptedPacket);
+        }
+
+        let mut bytes = [0; 2];
+        reader.read_exact(&mut bytes)?;
+        let namespace_bits = (bytes[0] & 0xC0) >> 6;
+        let namespace = match namespace_bits {
+            0 => NameSpace::GenICam,
+            2 => NameSpace::DeviceSpecific,
+            _ => {
+                println!("namespace = {} error", namespace_bits);
+                return Err(Error::CorruptedPacket);
+            }
+        };
+
+        let event_id = (bytes[0] & 0xF) as u16 | (bytes[1] as u16);
+
+        let timestamp = reader.read_u64()?;
+
+        let mut ev: [u8; EV_MAXSIZE] = [0; EV_MAXSIZE];
+        reader.read(&mut ev[0..ev_size as usize])?;
+
+        let checksum = get_cxp_crc(&reader.get_ref()[0..reader.position()]);
+        if reader.read_u32()? != checksum {
+            println!("crc error");
+            return Err(Error::CorruptedPacket);
+        }
+
+        Ok(DownConnPacket::Event {
+            conn_id,
+            packet_tag,
+            length,
+            ev_size,
+            namespace,
+            event_id,
+            timestamp,
+            ev,
+        })
+    }
+}
+
+trait CxpWrite {
+    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error>;
+
+    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error>;
+
+    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error>;
+
+    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error>;
+
+    fn write_u32(&mut self, value: u32) -> Result<(), Error>;
+}
+impl<Cursor: Write> CxpWrite for Cursor {
+    fn write_all_4x(&mut self, buf: &[u8]) -> Result<(), Error> {
+        for byte in buf {
+            self.write_all(&[*byte; 4])?;
+        }
+        Ok(())
+    }
+
+    fn write_4x_u8(&mut self, value: u8) -> Result<(), Error> {
+        self.write_all_4x(&[value])
+    }
+
+    fn write_4x_u16(&mut self, value: u16) -> Result<(), Error> {
+        let mut bytes = [0; 2];
+        NetworkEndian::write_u16(&mut bytes, value);
+        self.write_all_4x(&bytes)
+    }
+
+    fn write_4x_u32(&mut self, value: u32) -> Result<(), Error> {
+        let mut bytes = [0; 4];
+        NetworkEndian::write_u32(&mut bytes, value);
+        self.write_all_4x(&bytes)
+    }
+
+    fn write_u32(&mut self, value: u32) -> Result<(), Error> {
+        let mut bytes = [0; 4];
+        NetworkEndian::write_u32(&mut bytes, value);
+        self.write_all(&bytes)?;
+        Ok(())
+    }
+}
+
+#[derive(Debug)]
+pub enum UpConnPacket {
+    CtrlRead {
+        tag: Option<u8>,
+        addr: u32,
+        length: u32,
+    },
+    CtrlWrite {
+        tag: Option<u8>,
+        addr: u32,
+        length: u32,
+        data: [u8; DATA_MAXSIZE],
+    },
+    EventAck {
+        packet_tag: u8,
+    },
+}
+
+impl UpConnPacket {
+    pub fn write_to(&self, writer: &mut Cursor<&mut [u8]>) -> Result<(), Error> {
+        match *self {
+            UpConnPacket::CtrlRead { tag, addr, length } => {
+                match tag {
+                    Some(t) => {
+                        writer.write_4x_u8(0x05)?;
+                        writer.write_4x_u8(t)?;
+                    }
+                    None => {
+                        writer.write_4x_u8(0x02)?;
+                    }
+                }
+
+                let mut bytes = [0; 3];
+                NetworkEndian::write_u24(&mut bytes, length);
+                writer.write_all(&[0x00, bytes[0], bytes[1], bytes[2]])?;
+
+                writer.write_u32(addr)?;
+
+                // Section 9.6.2 (CXP-001-2021)
+                // only bytes after the first 4 are used in calculating the checksum
+                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
+                writer.write_u32(checksum)?;
+            }
+            UpConnPacket::CtrlWrite {
+                tag,
+                addr,
+                length,
+                data,
+            } => {
+                match tag {
+                    Some(t) => {
+                        writer.write_4x_u8(0x05)?;
+                        writer.write_4x_u8(t)?;
+                    }
+                    None => {
+                        writer.write_4x_u8(0x02)?;
+                    }
+                }
+
+                let mut bytes = [0; 3];
+                NetworkEndian::write_u24(&mut bytes, length);
+                writer.write_all(&[0x01, bytes[0], bytes[1], bytes[2]])?;
+
+                writer.write_u32(addr)?;
+                writer.write_all(&data[0..length as usize])?;
+
+                // Section 9.6.2 (CXP-001-2021)
+                // only bytes after the first 4 are used in calculating the checksum
+                let checksum = get_cxp_crc(&writer.get_ref()[4..writer.position()]);
+                writer.write_u32(checksum)?;
+            }
+            UpConnPacket::EventAck { packet_tag } => {
+                writer.write_4x_u8(0x08)?;
+                writer.write_4x_u8(packet_tag)?;
+            }
+        }
+        Ok(())
+    }
+}
+
+// DEBUG: use only
+//
+//
+//
+pub fn print_packet(pak: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len() / 4) {
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X},",
+            i + 1,
+            pak[i * 4],
+            pak[i * 4 + 1],
+            pak[i * 4 + 2],
+            pak[i * 4 + 3]
+        )
+    }
+    println!("]");
+    println!("============================================");
+}
+
+pub fn print_packetu32(pak: &[u32], k: &[u8]) {
+    println!("pak = [");
+    for i in 0..(pak.len()) {
+        let data: [u8; 4] = pak[i].to_le_bytes();
+        println!(
+            "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b},",
+            i + 1,
+            data[0],
+            data[1],
+            data[2],
+            data[3],
+            k[i],
+        )
+    }
+    println!("]");
+    println!("============================================");
+}

src/libboard_artiq/src/cxp_upconn.rs

@@ -0,0 +1,91 @@
+use core::slice;
+
+use embedded_hal::blocking::delay::DelayUs;
+use io::Cursor;
+use libboard_zynq::{println, timer::GlobalTimer};
+
+use crate::{cxp_proto,
+            mem::mem::CXP_MEM,
+            pl::csr::{self, CXP}};
+const BUF_LEN: usize = 0x800;
+
+pub fn tx_test(channel: u8, timer: &mut GlobalTimer) {
+    const LEN: usize = 4 * 100;
+    let mut pak_arr: [u8; LEN] = [0; LEN];
+
+    let channel = channel as usize;
+    unsafe {
+        (CXP[channel].upconn_trig_delay_write)(0x86);
+        (CXP[channel].upconn_linktrigger_write)(0x00);
+
+        // DEBUG: prepare the packet before tx enable to avoid overhead
+        preload_tx_packet(
+            channel as u8,
+            &cxp_proto::UpConnPacket::CtrlRead {
+                tag: None,
+                addr: 0,
+                length: 4,
+            },
+        );
+
+        csr::cxp_phys::upconn_tx_enable_write(1);
+        timer.delay_us(1);
+
+        // DEBUG: send ctrl packet or test
+        (CXP[channel].upconn_bootstrap_tx_write)(1);
+        (CXP[channel].upconn_bootstrap_tx_testseq_write)(1);
+
+        // DEBUG: Trigger packet (NOTE: disconnected in Gateware)
+        // (CXP[channel].upconn_trig_stb_write)(1); // send trig
+
+        // DEBUG: Trigger ACK packet
+        // (CXP[channel].upconn_ack_write)(1);
+
+        timer.delay_us(2000);
+        csr::cxp_phys::upconn_tx_enable_write(0);
+
+        // Collect data
+        let mut i: usize = 0;
+        match channel {
+            0 => {
+                while csr::cxp_phys::upconn_tx0_debug_buf_dout_valid_read() == 1 {
+                    pak_arr[i] = csr::cxp_phys::upconn_tx0_debug_buf_dout_pak_read();
+                    csr::cxp_phys::upconn_tx0_debug_buf_inc_write(1);
+                    i += 1;
+                    if i == LEN {
+                        break;
+                    }
+                }
+            }
+            1 => {
+                while csr::cxp_phys::upconn_tx1_debug_buf_dout_valid_read() == 1 {
+                    pak_arr[i] = csr::cxp_phys::upconn_tx1_debug_buf_dout_pak_read();
+                    csr::cxp_phys::upconn_tx1_debug_buf_inc_write(1);
+                    i += 1;
+                    if i == LEN {
+                        break;
+                    }
+                }
+            }
+            _ => {}
+        }
+
+        cxp_proto::print_packet(&pak_arr);
+    }
+}
+
+fn preload_tx_packet(channel: u8, packet: &cxp_proto::UpConnPacket) {
+    let channel = channel as usize;
+    unsafe {
+        while (CXP[channel].upconn_bootstrap_tx_busy_read)() == 1 {}
+        let ptr = CXP_MEM[channel].base as *mut u32;
+        let mut writer = Cursor::new(slice::from_raw_parts_mut(ptr as *mut u8, BUF_LEN));
+
+        packet.write_to(&mut writer).expect("unstable to write to tx mem");
+        // DEBUG:
+        println!("TX MEM after writing");
+        cxp_proto::print_packet(&writer.get_ref()[0..40]);
+
+        (CXP[channel].upconn_bootstrap_tx_word_len_write)(writer.position() as u16 / 4);
+    }
+}

src/libboard_artiq/src/lib.rs

@@ -3,6 +3,7 @@
 #![feature(naked_functions)]
 #![feature(asm)]
 
+extern crate byteorder;
 extern crate core_io;
 extern crate crc;
 extern crate embedded_hal;
@@ -25,7 +26,7 @@ pub mod fiq;
 #[cfg(feature = "target_kasli_soc")]
 pub mod io_expander;
 pub mod logger;
-#[cfg(has_drtio)]
+#[cfg(any(has_drtio, has_cxp_phys))]
 #[rustfmt::skip]
 #[path = "../../../build/mem.rs"]
 pub mod mem;
@@ -42,6 +43,19 @@ pub mod si5324;
 pub mod si549;
 use core::{cmp, str};
 
+#[cfg(has_cxp_phys)]
+pub mod cxp_downconn;
+#[cfg(has_cxp_phys)]
+pub mod cxp_upconn;
+
+pub mod cxp_proto;
+
+pub mod cxp_phys;
+
+pub mod cxp;
+
+pub mod cxp_ctrl;
+
 pub fn identifier_read(buf: &mut [u8]) -> &str {
     unsafe {
         pl::csr::identifier::address_write(0);

src/libksupport/src/cxp.rs

@@ -0,0 +1,224 @@
+use byteorder::{ByteOrder, NetworkEndian};
+use cslice::CMutSlice;
+use libboard_artiq::{cxp::{setup, MASTER_CHANNEL},
+                     cxp_ctrl,
+                     cxp_proto::DATA_MAXSIZE};
+
+// for downloading the XML files
+// TODO: change this to read bytes and accept TBytearray
+pub extern "C" fn cxp_read_words(addr: i32, val: &mut CMutSlice<i32>, with_tag: bool) {
+    let mut bytes: [u8; DATA_MAXSIZE] = [0; DATA_MAXSIZE];
+    cxp_ctrl::read_bytes(MASTER_CHANNEL, addr as u32, &mut bytes[..val.len() * 4], with_tag)
+        .unwrap_or_else(|e| panic!("CXP readu64 failure: {}", e));
+
+    for i in 0..val.len() {
+        val.as_mut_slice()[i] = NetworkEndian::read_u32(&bytes[i * 4..(i + 1) * 4]) as i32;
+    }
+}
+
+pub extern "C" fn cxp_readu32(addr: i32, with_tag: bool) -> i32 {
+    // TODO: use artiq_raise like i2c?
+    cxp_ctrl::read_u32(MASTER_CHANNEL, addr as u32, with_tag).unwrap_or_else(|e| panic!("CXP readu64 failure: {}", e))
+        as i32
+}
+
+pub extern "C" fn cxp_readu64(addr: i32, with_tag: bool) -> i64 {
+    // TODO: use artiq_raise like i2c?
+    cxp_ctrl::read_u64(MASTER_CHANNEL, addr as u32, with_tag).unwrap_or_else(|e| panic!("CXP read u64 failure: {}", e))
+        as i64
+}
+
+pub extern "C" fn cxp_writeu32(addr: i32, val: i32, with_tag: bool) {
+    // TODO: use artiq_raise like i2c?
+    cxp_ctrl::write_u32(MASTER_CHANNEL, addr as u32, val as u32, with_tag)
+        .unwrap_or_else(|e| panic!("CXP write u32 failure: {}", e));
+}
+
+pub extern "C" fn cxp_writeu64(addr: i32, val: i64, with_tag: bool) {
+    // TODO: use artiq_raise like i2c?
+    cxp_ctrl::write_u64(MASTER_CHANNEL, addr as u32, val as u64, with_tag)
+        .unwrap_or_else(|e| panic!("CXP write u64 failure: {}", e));
+}
+
+pub extern "C" fn cxp_setup() -> bool {
+    setup().unwrap()
+}
+
+// DEBUG: ONLY
+pub extern "C" fn cxp_debug_frame_print() {
+    use libboard_zynq::println;
+
+    use crate::pl::csr::{cxp_frame_pipeline, CXP};
+    const LEN: usize = 200;
+    let mut eop: [u8; LEN] = [0; LEN];
+    let mut pak_arr: [u32; LEN] = [0; LEN];
+    let mut k_arr: [u8; LEN] = [0; LEN];
+    let mut err: [u8; LEN] = [0; LEN];
+    let mut i: usize = 0;
+    unsafe {
+        while cxp_frame_pipeline::debug_out_dout_valid_read() == 1 {
+            pak_arr[i] = cxp_frame_pipeline::debug_out_dout_pak_read();
+            k_arr[i] = cxp_frame_pipeline::debug_out_kout_pak_read();
+            eop[i] = cxp_frame_pipeline::debug_out_eop_read();
+            err[i] = cxp_frame_pipeline::debug_out_crc_error_read();
+            // println!("received {:#04X}", pak_arr[i]);
+            cxp_frame_pipeline::debug_out_inc_write(1);
+            i += 1;
+            if i == LEN {
+                break;
+            }
+        }
+        // let channel: usize = 0;
+        // while (CXP[channel].downconn_debug_out_dout_valid_read)() == 1 {
+        //     pak_arr[i] = (CXP[channel].downconn_debug_out_dout_pak_read)();
+        //     k_arr[i] = (CXP[channel].downconn_debug_out_kout_pak_read)();
+        //     // println!("received {:#04X}", pak_arr[i]);
+        //     (CXP[channel].downconn_debug_out_inc_write)(1);
+        //     i += 1;
+        //     if i == LEN {
+        //         break;
+        //     }
+        // }
+        println!(
+            "Decode error = {}",
+            (CXP[MASTER_CHANNEL as usize].downconn_bootstrap_decoder_err_read)()
+        );
+        println!(
+            "Trigger ack = {}",
+            (CXP[MASTER_CHANNEL as usize].downconn_trigger_ack_read)()
+        );
+        if (CXP[MASTER_CHANNEL as usize].downconn_trigger_ack_read)() == 1 {
+            println!("Trigger ack clear");
+            (CXP[MASTER_CHANNEL as usize].downconn_trigger_ack_write)(1);
+        };
+    }
+    cxp_ctrl::print_decode_error(MASTER_CHANNEL);
+    if i > 0 {
+        print_packetu32(&pak_arr, &k_arr, &err, &eop, i as usize);
+    } else {
+        println!("No frame data received");
+    }
+}
+
+pub fn print_packetu32(pak: &[u32], k: &[u8], err: &[u8], eop: &[u8], len: usize) {
+    use libboard_zynq::println;
+    println!("pak = [");
+    let mut i_stream_id: usize = len + 1;
+    let mut i_pak_tag: usize = len + 1;
+    let mut i_size_0: usize = len + 1;
+    let mut i_size_1: usize = len + 1;
+    for i in 0..len {
+        let data: [u8; 4] = pak[i].to_be_bytes();
+        // if eop[i] == 1 {
+        //     if err[i] == 1 {
+        //         println!(
+        //             "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | eop crc error",
+        //             i + 1,
+        //             data[0],
+        //             data[1],
+        //             data[2],
+        //             data[3],
+        //             k[i],
+        //         );
+        //     } else {
+        //         println!(
+        //             "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | eop",
+        //             i + 1,
+        //             data[0],
+        //             data[1],
+        //             data[2],
+        //             data[3],
+        //             k[i],
+        //         );
+        //     }
+        //     i_stream_id = i + 1;
+        //     i_pak_tag = i + 2;
+        //     i_size_0 = i + 3;
+        //     i_size_1 = i + 4
+        // } else if i == i_stream_id {
+        //     println!(
+        //         "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | stream id",
+        //         i + 1,
+        //         data[0],
+        //         data[1],
+        //         data[2],
+        //         data[3],
+        //         k[i],
+        //     );
+        // } else if i == i_pak_tag {
+        //     println!(
+        //         "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | packet tag",
+        //         i + 1,
+        //         data[0],
+        //         data[1],
+        //         data[2],
+        //         data[3],
+        //         k[i],
+        //     );
+        // } else if i == i_size_0 {
+        //     println!(
+        //         "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | DsizeP[15:8]",
+        //         i + 1,
+        //         data[0],
+        //         data[1],
+        //         data[2],
+        //         data[3],
+        //         k[i],
+        //     );
+        // } else if i == i_size_1 {
+        //     println!(
+        //         "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | DsizeP[7:0]",
+        //         i + 1,
+        //         data[0],
+        //         data[1],
+        //         data[2],
+        //         data[3],
+        //         k[i],
+        //     );
+        // } else {
+        //     if err[i] == 1 {
+        //         println!(
+        //             "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | crc error",
+        //             i + 1,
+        //             data[0],
+        //             data[1],
+        //             data[2],
+        //             data[3],
+        //             k[i],
+        //         );
+        //     } else {
+        //         println!(
+        //             "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} |",
+        //             i + 1,
+        //             data[0],
+        //             data[1],
+        //             data[2],
+        //             data[3],
+        //             k[i],
+        //         );
+        //     }
+        if err[i] == 1 {
+            println!(
+                "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} | crc error",
+                i + 1,
+                data[0],
+                data[1],
+                data[2],
+                data[3],
+                k[i],
+            );
+        } else {
+            println!(
+                "{:#03}     {:#04X} {:#04X} {:#04X} {:#04X} | K {:04b} |",
+                i + 1,
+                data[0],
+                data[1],
+                data[2],
+                data[3],
+                k[i],
+            );
+        };
+    }
+    println!("]");
+    println!("============================================");
+}

src/libksupport/src/kernel/api.rs

@@ -11,6 +11,8 @@ use super::{cache,
             core1::rtio_get_destination_status,
             dma, linalg,
             rpc::{rpc_recv, rpc_send, rpc_send_async}};
+#[cfg(has_cxp_phys)]
+use crate::cxp;
 use crate::{eh_artiq, i2c, rtio};
 
 extern "C" {
@@ -126,6 +128,22 @@ pub fn resolve(required: &[u8]) -> Option<u32> {
         #[cfg(has_drtio)]
         api!(subkernel_await_message = subkernel::await_message),
 
+        // CoaXPress
+        #[cfg(has_cxp_phys)]
+        api!(cxp_read_words = cxp::cxp_read_words),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_readu32 = cxp::cxp_readu32),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_readu64 = cxp::cxp_readu64),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_writeu32 = cxp::cxp_writeu32),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_writeu64 = cxp::cxp_writeu64),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_setup = cxp::cxp_setup),
+        #[cfg(has_cxp_phys)]
+        api!(cxp_debug_frame_print = cxp::cxp_debug_frame_print),
+
         // Double-precision floating-point arithmetic helper functions
         // RTABI chapter 4.1.2, Table 2
         api!(__aeabi_dadd),

src/libksupport/src/lib.rs

@@ -35,6 +35,8 @@ pub mod rtio;
 #[path = "../../../build/pl.rs"]
 pub mod pl;
 
+#[cfg(has_cxp_phys)]
+pub mod cxp;
 
 #[derive(Debug, Clone)]
 pub struct RPCException {

src/libunwind/build.rs

@@ -23,6 +23,7 @@ mod llvm_libunwind {
         cfg.flag("--target=armv7-none-eabihf");
         cfg.flag("-O2");
         cfg.flag("-flto");
+        cfg.flag("-Wno-everything");
 
         cfg.flag("-std=c99");
         cfg.flag("-fstrict-aliasing");

src/runtime/src/main.rs

@@ -13,6 +13,8 @@ use core::cell::RefCell;
 
 use ksupport;
 use libasync::task;
+#[cfg(has_cxp_phys)]
+use libboard_artiq::cxp_phys;
 #[cfg(has_drtio_eem)]
 use libboard_artiq::drtio_eem;
 #[cfg(feature = "target_kasli_soc")]
@@ -150,5 +152,8 @@ pub fn main_core0() {
 
     task::spawn(ksupport::report_async_rtio_errors());
 
+    #[cfg(has_cxp_phys)]
+    cxp_phys::setup(&mut timer);
+
     comms::main(timer, cfg);
 }