forked from M-Labs/artiq-zynq
56 lines
1.6 KiB
Python
56 lines
1.6 KiB
Python
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from migen import *
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from misoc.interconnect.csr import *
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from functools import reduce
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from itertools import combinations
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from operator import or_, and_
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class Voter(Module):
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def __init__(self):
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self.data_4x = Signal(32)
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self.k_4x = Signal(4)
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# Section 9.2.2.1 (CXP-001-2021)
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# decoder should immune to single bit errors when handling duplicated characters
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self.char = Signal(8)
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self.k = Signal()
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# majority voting
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char = [[self.data_4x[i*8:(i+1)*8], self.k_4x[i]] for i in range(4)]
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voter = [Record([("data", 8), ("k", 1)]) for _ in range(4)]
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# stage 1
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for i, code in enumerate(combinations(char, 3)):
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self.sync += [
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voter[i].data.eq(reduce(and_, [c[0] for c in code])),
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voter[i].k.eq(reduce(and_, [c[1] for c in code])),
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]
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# stage 2
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self.sync += [
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self.char.eq(reduce(or_, [v.data for v in voter])),
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self.k.eq(reduce(or_, [v.k for v in voter])),
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]
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dut = Voter()
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def check_case(data_4x, k_4x, char, k):
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yield dut.data_4x.eq(data_4x)
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yield dut.k_4x.eq(k_4x)
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yield
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yield
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yield
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print(f"char = {yield dut.char:#X} k = {yield dut.k:#X}")
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assert (yield dut.char) == char and (yield dut.k) == k
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def testbench():
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yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
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yield from check_case(0xFFFFFF00, 0b1110, 0xFF, 1)
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yield from check_case(0xFFFFF00f, 0b0001, 0xFF, 0)
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yield from check_case(0xFFFFFFFF, 0b1111, 0xFF, 1)
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run_simulation(dut, testbench())
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