ljstephenson
  • Joined on 2022-03-23
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ljstephenson commented on issue M-Labs/artiq-zynq#246

satellite: SYS CLK did not switch

Just tested the newly built zc706 `boot.bin` for 125 and 100 MHz separately, both booting fine, thanks!

2023-10-07 02:01:32 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#246

satellite: SYS CLK did not switch

We use the 100 MHz directly with `rtio_clock = ext0_bypass`, i.e. we aren't making a 125 MHz RTIO clock with PLL (I wasn't aware this was an option, although it's not one we're likely to use…

2023-10-06 01:02:21 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#246

satellite: SYS CLK did not switch

@sb10q I've confirmed (unsurprisingly) that this affects Kasli-SoC DRTIO masters also; the same commit introduces the breakage. This is with the external clock running at 100 MHz. Just to push…

2023-10-05 07:21:10 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#246

satellite: SYS CLK did not switch

I'm running into this same issue on ZC706 nist qc2 master variant, attempting to boot from SD with an external clock. The most recent build 151734 does not boot. The first failing build is…

2023-10-04 08:29:20 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#205

Feature Request: EdgeCounters for NIST QC2 gateware

One of my colleagues has been trying to test the gateware and ran into the following problem; calling `fetch_count` on the counter hangs as if there was no input to fetch, despite an earlier call…

2022-11-30 02:40:20 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#205

Feature Request: EdgeCounters for NIST QC2 gateware

Still failing with same error after I exchange /opt/ for my path to Xilinx. See attached diff for the changes I made (dummy path in the diff, but you get the picture). Note as I mentioned that…

2022-11-04 00:46:20 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#205

Feature Request: EdgeCounters for NIST QC2 gateware

That said, building with the same command from artiq-zynq/master works fine, so my Vivado installation isn't completely broken. Also my nix-fu isn't completely up to scratch: I see that the…

2022-11-03 11:35:10 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#205

Feature Request: EdgeCounters for NIST QC2 gateware

Build failed, but it seems like it may be something weird with my system. Freshly cloned from your fork, I get: ``` $ nix build .#zc706-nist_qc2_master-sd error: builder for '/nix/store/aqr0b6…

2022-11-03 11:15:30 +08:00

ljstephenson opened issue M-Labs/artiq-zynq#205

Feature Request: EdgeCounters for NIST QC2 gateware

2022-11-03 10:00:49 +08:00

ljstephenson reopened issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

2022-05-27 05:44:49 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

@mwojcik @sb10q we just saw another hang with a similar experiment (accessing devices from a list) - going back to a test setup to try to reproduce consistently. Using zc706 DRTIO master build 123830.

2022-05-27 05:44:48 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#189

Moninj connection causes core panic on zc706

Tested 1f95b5970c93c3e047c4cbd9b1933b9c64b7e22b on both a live system and another with no satellite, I'm still getting the same behaviour as before (live system: unpingable, no satellite: 8ms error…

2022-05-19 05:39:56 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#189

Moninj connection causes core panic on zc706

Built from e34381094b to test; at the moment I have a zc706 test setup with no satellite, and our live system with a single satellite. I'm working on having a satellite for the test setup to avoid…

2022-05-14 05:48:54 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#189

Moninj connection causes core panic on zc706

This happens only with satellite data in the device_db, good catch; I've attached a minimal device_db that still elicits a crash, regardless of whether the satellite is connected. I'll try the…

2022-05-14 01:33:28 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#189

Moninj connection causes core panic on zc706

I don't appear to have the same issue with https://nixbld.m-labs.hk/build/121703, so this seems to be DRTIO gateware related.

2022-05-13 06:00:20 +08:00

ljstephenson opened issue M-Labs/artiq-zynq#189

Moninj connection causes core panic on zc706

2022-05-13 02:36:53 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

efc432352e appears to have fixed the hangs so far - thanks, sounds like it was a bear to identify! I'll continue to keep an eye out for any recurrences.

2022-05-04 01:24:38 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

@sb10q the kernel hangs are pretty catastrophic: at the moment the DRTIO gateware is unusable because of the hangs. There doesn't appear to be a workaround at the moment, since even accessing the…

2022-04-30 06:38:17 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

Same problem with ACPKI (https://nixbld.m-labs.hk/build/121087). Also not specific to DDSs; an exactly analogous experiment using 12 TTLs and `ttl.output()` in place of `dds.init()` failed in the…

2022-04-28 00:27:04 +08:00

ljstephenson commented on issue M-Labs/artiq-zynq#188

ZC706/QC2 accessing devices from list causes hang/crash

Same story with https://nixbld.m-labs.hk/build/121055 (again no hardware connected) BUT it doesn't hang or crash with the loop unrolled, i.e. ``` from artiq.experiment import * class…

2022-04-27 06:46:49 +08:00