linuswck

linuswck pushed to rename_drtio_transceiver_to_gt_drtio at linuswck/artiq-zynq

2023-08-28 12:55:14 +08:00

linuswck created branch rename_drtio_transceiver_to_gt_drtio in linuswck/artiq-zynq

2023-08-28 12:55:14 +08:00

linuswck created repository linuswck/artiq-zynq

2023-08-28 12:48:10 +08:00

linuswck commented on issue M-Labs/artiq-zynq#246

2023-08-14 11:24:30 +08:00

I'm pretty sure there is, it's just not obvious. Did you check the unisim model code?

I cannot find any info useful in the [Xilinx unisim library](https://github.com/Xilinx/XilinxUnisimLibrary…

linuswck commented on issue M-Labs/artiq-zynq#246

2023-08-11 15:35:37 +08:00

Surely, there must be some information about it somewhere?

The max PLL Lock time is 1ms and this info locates inside the AC/DC Switching Characteristics [datasheet](https://docs.xilinx…

linuswck commented on issue M-Labs/artiq-zynq#246

2023-08-11 13:16:41 +08:00

I will test it further on the master branch or other commit.

I can confirm that the fix works on the latest master branch commit. artiq-zynq: 583b629b40d748e776c1b714d09dbbee132b33dc

linuswck commented on issue M-Labs/artiq-zynq#246

2023-08-11 13:08:02 +08:00

I do not think the minimum value can be computed.

Firstly, the CPLL inside GTXE2_Channel does not have specification on the CPLL lock time. (In, UG476 Page 64, "CPLL Reset" session does not…

linuswck commented on issue M-Labs/artiq-zynq#246

2023-08-11 11:58:33 +08:00

I only tried network boot when I work on this PR, which should resolve this CLK does not switch problem. SD Card Boot was not tested on…

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