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kirdy
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105 Commits 2 Branches 0 Tags 29 MiB
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35 Commits

Author SHA1 Message Date
linuswck 2cbab29c4e sch, pcb: Add LEDs and TPs to Critical Power Rails 2023-11-27 17:37:52 +08:00
linuswck c59eccaa7d sch, pcb: add 0R for TEC Vref Ouput 
- For debugging if needed
 2023-11-27 17:37:52 +08:00
linuswck db54e6cfa8 sch, pcb:Edit PCB shape for connectors to protrude 
- Connectors now protrude the front panel
- Align the connectors by the outline generated from 3D Model
- Update the front panel symbol to include the two mounting holes
 2023-11-27 17:37:52 +08:00
linuswck b901f84d0a sch, pcb: Add PWR, POE_PWR netclasses 2023-11-21 11:46:46 +08:00
linuswck de7c27c21f sch, pcb: Add mounting holes for Kirdy LD Adapter 2023-11-17 15:42:43 +08:00
linuswck 41db8612c0 pcb: relocate switches for better accessibility 
- modulation depth SW and termination SW are relocated
 2023-11-15 17:12:05 +08:00
linuswck de3e034c7a Add Front Panel, Kirdy LD Adapter 3D models 
- Update sch, pcb, sym lib, footrprint lib
- Position of Kirdy LD Adapter is relocated so that it is symmetric
 2023-11-15 17:11:51 +08:00
linuswck 9f3793c8fb pcb: Add 3D Models 2023-11-10 17:32:29 +08:00
linuswck 0b99a8f119 sch, pcb: Correct MFR/PN and optimize BOM 2023-11-10 15:18:22 +08:00
linuswck 5ad5914748 sch, pcb: exclude MHs and soldering JP from BOM 2023-11-09 15:24:07 +08:00
linuswck a30ac45c5f pcb: Remove "designed by" silkscreen 2023-11-08 11:53:18 +08:00
linuswck 13b5f661c5 pcb: Fix TEC Polarity Connections to Header 
- Fix Issue #27
 2023-11-08 11:53:07 +08:00
linuswck 2a6ad78f51 pcb: Finish Layout for rev0_3 
- Assign MFR_PN for all Components
- schematics changes:
  - drivestage: Add Switch to optionally enable Modulation Signal Termination
  -             Add alternate Precision Power Resistor
  -             Modify the RC network values at TIA LPF Output
  - MCU: Add Redundant 2.54mm pitch Programming Header
  - thermostat: Duplicate the power filter network for alternate Temperature ADC
 2023-11-02 15:24:26 +08:00
linuswck 5ffc2a1865 pcb: migrate to kicad 7 2023-10-25 17:35:58 +08:00
Alex Wong Tat Hang ad982265b2 improve relay power circuitry 2022-09-09 14:37:19 +08:00
Alex Wong Tat Hang 3715d93d5e clean up 2022-09-08 03:46:38 +08:00
Alex Wong Tat Hang 29cfbc9c4e finish v2 layout 2022-09-08 03:35:59 +08:00
Alex Wong Tat Hang be08d4518c some layout 2022-09-06 00:15:25 +08:00
Alex Wong Tat Hang 6aa57e04a3 update palcement 2022-09-04 23:27:58 +08:00
Alex Wong Tat Hang facb6df2cf placement v2 2022-09-04 23:06:16 +08:00
Alex Wong Tat Hang 78c8d1f1c6 fix eth 2022-09-03 19:00:29 +08:00
Alex Wong Tat Hang 82f609d00a sync 2022-08-31 21:11:43 +08:00
TopQuark12 65667ce44f v 0.2 schematics 2022-08-18 15:47:33 +08:00
Alex Wong Tat Hang 5227b8738b add V01 production files, bug fixes 2022-08-05 05:04:05 +08:00
Alex Wong Tat Hang 2ad7578972 minor adjustments 2022-07-08 01:44:56 +08:00
Alex Wong Tat Hang 50f5d78387 shove trace 2022-07-07 17:07:23 +08:00
Alex Wong Tat Hang 0c9d60ec79 polish 2022-07-07 16:54:30 +08:00
Alex Wong Tat Hang 757f8c2ebb passes DRC 2022-07-07 02:03:50 +08:00
Alex Wong Tat Hang b115f89f23 roughly done 2022-07-07 01:36:20 +08:00
Alex Wong Tat Hang ea71003c8b more routing 2022-07-06 22:24:28 +08:00
Alex Wong Tat Hang 79de11fd16 routing, bom update 2022-07-06 20:30:22 +08:00
Alex Wong Tat Hang beab99681b complete placement 2022-07-05 19:35:37 +08:00
Alex Wong Tat Hang 5063de718f add bom, finish rough placement 2022-07-05 00:50:06 +08:00
TopQuark12 1860500f11 rough placement 2022-07-04 18:39:52 +08:00
topquark12 0f59b6aa38 add project 2022-06-12 20:30:00 +08:00