2023-12-20 12:08:48 +08:00
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use core::u16;
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use crate::thermostat::ad5680;
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2023-12-21 13:13:06 +08:00
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use fugit::KilohertzU32;
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2023-12-20 12:08:48 +08:00
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use stm32f4xx_hal::{
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adc::{
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config::{self, AdcConfig},
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Adc,
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},
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gpio::{gpioa::*, gpiob::*, gpioc::*, Alternate, Analog, Output, PushPull},
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hal::{self, blocking::spi::Transfer, digital::v2::OutputPin},
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2023-12-20 12:08:48 +08:00
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pac::{ADC1, SPI1, TIM4},
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spi::{NoMiso, Spi, TransferModeNormal},
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2024-01-09 16:53:34 +08:00
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timer::pwm::PwmChannel,
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};
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use uom::si::{
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electric_potential::millivolt,
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f64::ElectricPotential,
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ratio::ratio,
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};
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2023-12-21 13:13:06 +08:00
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pub const PWM_FREQ_KHZ: KilohertzU32 = KilohertzU32::from_raw(20);
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pub trait ChannelPins {
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type DacSpi: Transfer<u8>;
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type DacSync: OutputPin;
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type ShdnPin: OutputPin;
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type VRefPin;
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type ItecPin;
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type DacFeedbackPin;
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type VTecPin;
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type MaxVPin;
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type MaxIPosPin;
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type MAXINegPin;
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}
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pub struct Channel0;
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impl ChannelPins for Channel0 {
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type DacSpi = DacSpi;
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type DacSync = DacSync;
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type ShdnPin = PA5<Output<PushPull>>;
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type VRefPin = PA6<Analog>;
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type ItecPin = PB1<Analog>;
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type DacFeedbackPin = PC0<Analog>;
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type VTecPin = PB0<Analog>;
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type MaxVPin = PwmChannel<TIM4, 1>;
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type MaxIPosPin = PwmChannel<TIM4, 2>;
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type MAXINegPin = PwmChannel<TIM4, 0>;
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}
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pub struct MAX1968Phy<C: ChannelPins> {
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pub dac: ad5680::Dac<C::DacSpi, C::DacSync>,
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pub shdn: C::ShdnPin,
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pub vref_pin: C::VRefPin,
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pub itec_pin: C::ItecPin,
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pub dac_feedback_pin: C::DacFeedbackPin,
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pub vtec_pin: C::VTecPin,
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pub max_v: C::MaxVPin,
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pub max_i_pos: C::MaxIPosPin,
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pub max_i_neg: C::MAXINegPin,
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}
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pub struct MAX1968PinSet<C: ChannelPins> {
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pub dac: ad5680::Dac<C::DacSpi, C::DacSync>,
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pub shdn: C::ShdnPin,
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pub vref_pin: C::VRefPin,
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pub itec_pin: C::ItecPin,
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pub dac_feedback_pin: C::DacFeedbackPin,
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pub vtec_pin: C::VTecPin,
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pub max_v: C::MaxVPin,
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pub max_i_pos: C::MaxIPosPin,
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pub max_i_neg: C::MAXINegPin,
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}
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type DacSpi = Spi<SPI1, (PB3<Alternate<5>>, NoMiso, PB5<Alternate<5>>), TransferModeNormal>;
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type DacSync = PB4<Output<PushPull>>;
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pub struct MAX1968 {
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// settings
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pub phy: MAX1968Phy<Channel0>,
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pub pins_adc: Adc<ADC1>,
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}
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pub enum PwmPinsEnum {
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MaxV,
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MaxPosI,
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MaxNegI,
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}
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pub enum AdcReadTarget {
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VREF,
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DacVfb,
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ITec,
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VTec,
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}
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impl<C: ChannelPins> MAX1968Phy<C> {
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pub fn new(pins: MAX1968PinSet<C>) -> Self {
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MAX1968Phy {
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dac: pins.dac,
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shdn: pins.shdn,
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vref_pin: pins.vref_pin,
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itec_pin: pins.itec_pin,
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dac_feedback_pin: pins.dac_feedback_pin,
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vtec_pin: pins.vtec_pin,
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max_v: pins.max_v,
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max_i_pos: pins.max_i_pos,
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max_i_neg: pins.max_i_neg,
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}
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}
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}
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impl MAX1968 {
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pub fn new(phy_ch0: MAX1968Phy<Channel0>, adc1: ADC1) -> Self {
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let config = AdcConfig::default()
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.clock(config::Clock::Pclk2_div_8)
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.default_sample_time(config::SampleTime::Cycles_480);
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2024-01-24 17:03:06 +08:00
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// Do not set reset RCCs as it causes other ADCs' clock to be disabled
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let mut pins_adc = Adc::adc1(adc1, false, config);
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pins_adc.calibrate();
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MAX1968 {
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phy: phy_ch0,
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pins_adc: pins_adc,
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}
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}
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2024-01-22 12:24:19 +08:00
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// Return the calibrated VDDA Voltage
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// Can be used to set reference voltage for other ADC
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pub fn get_calibrated_vdda(&mut self) -> u32 {
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self.pins_adc.reference_voltage()
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}
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pub fn power_down(&mut self) {
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self.phy.shdn.set_low();
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}
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pub fn power_up(&mut self) {
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self.phy.shdn.set_high();
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}
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2024-01-05 15:00:50 +08:00
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pub fn set_dac(&mut self, voltage: ElectricPotential, dac_out_v_max: ElectricPotential) -> ElectricPotential {
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let value = ((voltage / dac_out_v_max).get::<ratio>()
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* (ad5680::MAX_VALUE as f64)) as u32;
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self.phy.dac.set(value).unwrap();
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// TODO: Store the set-ed DAC Voltage Value
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voltage
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}
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// AN4073: ADC Reading Dispersion can be reduced through Averaging
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// Upon test, 16 Point Averaging = +-3 LSB Dispersion
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pub fn adc_read(&mut self, adc_read_target: AdcReadTarget, avg_pt: u16) -> ElectricPotential {
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let mut sample: u32 = 0;
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sample = match adc_read_target {
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AdcReadTarget::VREF => {
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for _ in (0..avg_pt).rev() {
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sample += self.pins_adc.convert(
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&self.phy.vref_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480,
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) as u32;
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}
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sample / avg_pt as u32
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}
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AdcReadTarget::DacVfb => {
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for _ in (0..avg_pt).rev() {
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sample += self.pins_adc.convert(
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&self.phy.dac_feedback_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480,
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) as u32;
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}
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sample / avg_pt as u32
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}
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AdcReadTarget::ITec => {
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for _ in (0..avg_pt).rev() {
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sample += self.pins_adc.convert(
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&self.phy.itec_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480,
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) as u32;
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}
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sample / avg_pt as u32
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}
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AdcReadTarget::VTec => {
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for _ in (0..avg_pt).rev() {
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sample += self.pins_adc.convert(
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&self.phy.vtec_pin,
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stm32f4xx_hal::adc::config::SampleTime::Cycles_480,
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) as u32;
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}
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sample / avg_pt as u32
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}
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};
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let mv = self.pins_adc.sample_to_millivolts(sample as u16);
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ElectricPotential::new::<millivolt>(mv as f64)
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}
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2024-01-04 17:13:46 +08:00
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pub fn set_pwm(&mut self, pwm_pin: PwmPinsEnum, duty: f64, max_duty: f64) -> f64 {
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fn set<P: hal::PwmPin<Duty = u16>>(pin: &mut P, duty: f64) -> f64 {
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let max = pin.get_max_duty();
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let value = ((duty * (max as f64)) as u16).min(max);
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pin.set_duty(value);
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pin.enable();
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value as f64 / (max as f64)
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}
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let duty = duty.min(max_duty);
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match pwm_pin {
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PwmPinsEnum::MaxV => set(&mut self.phy.max_v, duty),
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PwmPinsEnum::MaxPosI => set(&mut self.phy.max_i_pos, duty),
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PwmPinsEnum::MaxNegI => set(&mut self.phy.max_i_neg, duty),
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}
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}
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}
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